Three dimensional non-volatile memory device and method of manufacturing the same
A three dimensional non-volatile memory structure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel insulating layer formed to surround the channel, a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers, and a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates.
1. A three dimensional non-volatile memory structure, comprising:
a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate;
a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates;
a tunnel insulating layer formed to surround the channel;
a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers; and
a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates.
2. The three dimensional non-volatile memory structure of claim 1 , wherein the plurality of interlayer dielectric layers has a thickness smaller than the plurality of control gates.
3. The three dimensional non-volatile memory structure of claim 1 , wherein each of the floating gates contacts a respective one of the control gates through the charge blocking layer at at least two interfacing surfaces.
4. The three dimensional non-volatile memory structure of claim 1 , wherein the floating gate includes a first region contacting the tunnel insulating layer and a second region contacting the interlayer dielectric layer through the charge blocking layer, and a thickness of the first region is substantially same to a thickness of the interlayer dielectric layer and a thickness of the second region is greater than a thickness of the interlayer dielectric layer.
5. The three dimensional non-volatile memory structure of claim 4 , wherein a thickness of the second region is greater than a length of a contacting face between the floating gate and the tunnel insulating layer.
6. The three dimensional non-volatile memory structure of claim 1 , wherein each of a plurality of memory cells stacked along the channel comprises:
a floating gate of the floating gates; and
two adjacent ones of the control gates that are formed over and under the floating gate, respectively.
7. The three dimensional non-volatile memory structure of claim 6 , wherein adjacent memory cells of the plurality of memory cells share a control gate of the control gates.
8. The three dimensional non-volatile memory structure of claim 1 , further comprising an air gap formed between adjacent ones of the plurality of control gates.
9. A memory system, comprising a memory controller and a non-volatile memory device having the three dimensional non-volatile memory structure of claim 1 ,
wherein the three dimensional non-volatile memory structure is configured to be controlled by the memory controller.
10. A three dimensional non-volatile memory structure, comprising:
a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate; and
a plurality of floating gates coupled to the control gates through a charge blocking layer and spaced apart from each other through the control gates that are alternatively disposed with the floating gates, wherein the control gates are thinner at regions placed between the floating gates than other regions placed between the dielectric layers.
11. The three dimensional non-volatile memory structure of claim 10 , wherein memory cells each include two immediately adjacent ones of the control gates and a floating gate placed between the two control gates and two immediately adjacent ones of the memory cells share a control gate.
12. The three dimensional non-volatile memory structure of claim 10 , further comprising:
a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates; and
a tunnel insulating layer formed to surround the channel.
13. The three dimensional non-volatile memory structure of claim 10 , wherein the control gates each have regions with different thicknesses at a surface contacting the charge blocking layer.
14. The three dimensional non-volatile memory structure of claim 10 , wherein the floating gate includes a first region contacting a tunnel insulating layer and a second region contacting the interlayer dielectric layer through the charge blocking layer, and a thickness of the first region is substantially same to a thickness of the interlayer dielectric layer and a thickness of the second region is greater than a thickness of the interlayer dielectric layer.
15. The three dimensional non-volatile memory structure of claim 10 , wherein the floating gate has a T shape.
16. The three dimensional non-volatile memory structure of claim 10 , wherein the plurality of interlayer dielectric layers has a thickness smaller than the plurality of control gates.
17. The three dimensional non-volatile memory structure of claim 10 , further comprising an air gap formed between adjacent ones of the plurality of control gates.