ADC with enhanced and/or adjustable accuracy
An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.
1. An analog-to-digital-converter comprising:
an input signal connector for receiving an input analog signal;
an output signal port;
two or more sub-ADCs, each sampling the analog input signal at the same point in time;
and a digital signal processing block, whereas the result from each sub-ADC is combined by the digital signal processing block to output data at the output signal port with increased performance.
2. An analog-to-digital-converter according to claim 1 where the analog input signal is passed through separate blocks prior to being applied at the input of each sub-ADC.
3. An analog-to-digital-converter according to claim 1 further comprising:
means to enable and disable the functionality of each sub-ADC individually;
and wherein the digital signal processing block has the ability to select the number of sub-ADCs used to generate the output data thereby adjusting the total performance.
4. An analog-to-digital-converter according to claim 1 , wherein the digital signal processing block calculates the average of the results from each sub-ADC.
5. An analog-to-digital-converter according to claim 4 , wherein calculating the average comprises summing the results from each sub-ADC and truncating the sum to a given number of bits.
6. A method of operating an analog-to-digital-converter, comprising:
receiving an input analog signal;
sampling the analog input signal at the same point in time using two or more sub-ADCs; and
combining the result from each sub-ADC to produce output data with increased performance.
7. The method of claim 6 , further comprising passing the analog input signal through separate blocks prior to applying it at the input of each sub-ADC.
8. The method of claim 6 , further comprising disabling the functionality of one or more selected sub-ADCs individually, thereby adjusting the totalperformance.
9. The method of claim 6 , wherein combining the result comprises calculating the average of the results from each sub-ADC.
10. The method of claim 9 , wherein calculating the average comprises summing the results from each sub-ADC and truncating the sum to a given number of bits.