IP Library Granted Patent US 8,749,906
Granted Patent B2
US 8,749,906 · App. 13/893,742 · Granted Jun 10, 2014

Systems and methods for improved servo data operation

Inventor: Nayak Ratnakar Aravind (Allentown, PA)
Assignee: Agere Systems Inc
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,749,906
App. No.
13/893,742
Granted
Jun 10, 2014
Kind
B2
Abstract

Various embodiments of the present invention provide systems, methods and media formats for efficiently determining a position error of a head in relation to a storage medium. In one case, a system is disclosed that includes a storage medium with a series of data. The series of data includes a first defined marker and a second defined marker located a distance from the first defined marker, and position location data. The systems further include a first detector circuit that is operable to detect the first defined marker and to establish a location of the first defined marker, and a second detector circuit that is operable to detect the second defined marker and to establish a location of the second defined marker. The systems further include an error calculation circuit and an interpolation circuit. The error calculation circuit is operable to calculate an interpolation offset based at least in part on the location of the first defined marker and the location of the second defined marker. The interpolation circuit is operable to interpolate the position location data and to provide an interpolated position location data.

Claims (44)

1. A system for efficiently determining a position error of a head in relation to a storage medium, the system comprising:

a detection circuit operable to:

detect a first defined marker in a series of data and to establish a location of the first defined marker; and

detect a second defined marker in the series of data a defined distance from the first defined marker, and to establish a location of the second defined marker; and

an error calculation circuit operable to calculate an interpolation offset based at least in part on the location of the first defined marker and the location of the second defined marker.

2. The system of claim 1 , wherein the detection circuit comprises:

a first detector circuit operable to detect the first defined marker and to establish the location of the first defined marker; and

a second detector circuit operable to detect the second defined marker in the series of data the defined distance from the first defined marker, and to establish the location of the second defined marker.

3. The system of claim 1 , wherein the system further comprises:

an interpolation circuit operable to interpolate a position location data in the series of data, and to provide an interpolated position location data.

4. The system of claim 3 , wherein the system is implemented as part of a storage device, wherein the storage device includes:

a storage medium including the series of data.

5. The system of claim 1 , wherein the system further comprises:

a burst demodulation circuit operable to generate a position error signal based at least in part on the interpolated position location data.

6. The system of claim 3 , wherein the series of data is sector data including a preamble pattern, wherein the first defined marker is a first sector address mark, wherein the second defined marker is a second sector address mark, and wherein the system further includes a signal receiving circuit including:

an analog to digital converter that samples an analog input using a sampling clock operating at a frequency and a phase to create the series of samples; and

a preamble detector and clock recovery circuit operable to detect the preamble pattern within the sector data and to adjust at least one of the frequency and the phase based on the preamble pattern to create an adjusted sampling clock.

7. The system of claim 6 , wherein the position location data includes at least a first burst pattern and a second burst pattern, wherein the first sector address mark is located after the preamble pattern and before the first burst pattern, and wherein the second sector address mark is located after the first burst pattern and before the second burst pattern.

8. The system of claim 7 , wherein the sector data includes a Gray code, and wherein the Gray code is located after the first sector address mark and before the second sector address mark.

9. The system of claim 1 , wherein the system is implemented as part of an integrated circuit.

10. The system of claim 3 , wherein the location of the first defined marker includes a combination of fractional distance and an integer distance from a reference location.

11. A method for efficient determination of a position error, the method comprising:

receiving the series of data, wherein the series of data includes a first defined marker, a second defined marker located a distance from the first defined marker, and a position location data;

detecting the first defined marker;

identifying a first location of the first defined marker;

detecting the second defined marker;

identifying a second location of the second defined marker;

calculating an interpolation offset based at least in part on the first location and the second location;

interpolating the position location data based on the interpolation offset to create interpolated position location data; and

determining a position error using the interpolated position location data.

12. The method of claim 11 , wherein the series of data is sector data including a preamble pattern, wherein the first defined marker is a first sector address mark, wherein the second defined marker is a second sector address mark, and wherein receiving the series of data includes:

receiving an analog input including the sector data;

sampling the analog input using a sampling clock operating at a frequency and a phase to generate at least a first portion of the sector data;

detecting the preamble pattern within the sector data;

adjusting at least one of the frequency and the phase based on the preamble pattern to create an adjusted sampling clock; and

sampling the analog input using the adjusted sampling clock to generate at least a second portion of the sector data.

13. The method of claim 12 , wherein the interpolation offset is operable to at least in part compensate for a phase error in the adjusted sampling clock.

14. The method of claim 12 , wherein the first sector address mark is the same as the second sector address mark.

15. The method of claim 12 , wherein the position location data includes at least a first burst pattern and a second burst pattern, wherein the first sector address mark is located after the preamble pattern and before the first burst pattern, and wherein the second sector address mark is located after the first burst pattern and before the second burst pattern.

16. The method of claim 15 , wherein the sector data further includes a Gray code, and wherein the Gray code is located after the first sector address mark and before the second sector address mark.

17. The method of claim 12 , wherein the position location data includes at least a first burst pattern, a second burst pattern and a third burst pattern, wherein the first sector address mark is located after the preamble pattern and before the first burst pattern, and wherein the second sector address mark is located after the second burst pattern and before the third burst pattern.

18. The method of claim 12 , wherein the sector data is a first sector data, wherein the storage medium further includes a second sector data including the same preamble pattern, first sector address mark and second sector address mark.

19. The method of claim 12 , wherein identifying the first location of the first sector address mark includes performing a first fractional location calculation, and wherein identifying the second location of the second sector address mark includes performing a second fractional location calculation.

20. The method of claim 12 , wherein calculating the interpolation offset includes subtracting the first location from the second location and dividing the result by the distance.

Assignments (11)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2013
From: ARAVIND, NAYAK RATNAKAR
To: AGERE SYSTEMS INC.
Reel/Frame 030412/0351 →
Continuity (2)
Continuation 12992940
Related Publication 20130250745A1 · Sep 26, 2013