Scheduling in a multicore architecture

1. A method of scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein at least one processor element comprises reconfigurable logic, the method comprising:

providing a plurality of executable transaction schedulers, each executable transaction scheduler comprising a scheduling algorithm for determining a most eligible executable transaction for execution from a number of candidate executable transactions;

linking the executable transaction schedulers together to form a multilevel scheduler;

providing a configuration queue of executable transactions for a first configuration of the reconfigurable logic, the executable transactions allocated to and ready for execution by the reconfigurable logic;

outputting a most eligible executable transaction from the multilevel scheduler to the configuration queue;

outputting the most eligible executable transaction from the configuration queue to the reconfigurable processor element for execution when the reconfigurable logic is configured according to the first configuration; and

reconfiguring the reconfigurable logic according to a second configuration when a pre-determined threshold is reached.

2. The method of claim 1 , wherein reconfiguring the reconfigurable logic comprises:

stopping the output of executable transactions from the configuration queue associated with the first configuration;

reconfiguring the reconfigurable logic according to the second configuration;

providing a second configuration queue of executable transactions for the second configuration, the executable transactions of the second configuration queue allocated to and ready for execution by the reconfigurable logic; and

outputting the executable transactions of the second configuration queue to the reconfigurable processor element for execution.

3. The method of claim 1 , wherein the reconfigurable logic is a memory.

4. The method of claim 1 , wherein the pre-determined threshold is a maximum time allowed before a particular executable transaction must be executed.

5. The method of claim 1 , wherein the second configuration is selected based on a length of a configuration queue associated with the second configuration.

6. The method of claim 5 , wherein the second configuration is selected in response to being associated with the longest configuration queue.

7. A non-transitory computer-readable storage medium comprising computer-executable instructions for scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein at least one processor element comprises reconfigurable logic, the instructions, when executed, configured to:

provide a plurality of executable transaction schedulers, each executable transaction scheduler comprising a scheduling algorithm for determining a most eligible executable transaction for execution from a number of candidate executable transactions;

link the executable transaction schedulers together to form a multilevel scheduler;

provide a configuration queue of executable transactions for a first configuration of the reconfigurable logic, the executable transactions allocated to and ready for execution by the reconfigurable logic;

output a most eligible executable transaction from the multilevel scheduler to the configuration queue;

output the most eligible executable transaction from the configuration queue to the reconfigurable processor element for execution when the reconfigurable logic is configured according to the first configuration; and

reconfigure the reconfigurable logic according to a second configuration when a pre-determined threshold is reached.

8. The non-transitory computer-readable storage medium of claim 7 , wherein reconfiguring the reconfigurable logic comprises:

stopping the output of executable transactions from the configuration queue associated with the first configuration;

reconfiguring the reconfigurable logic according to the second configuration;

providing a second configuration queue of executable transactions for the second configuration, the executable transactions of the second configuration queue allocated to and ready for execution by the reconfigurable logic; and

outputting the executable transactions of the second configuration queue to the reconfigurable processor element for execution.

9. The non-transitory computer-readable storage medium of claim 7 , wherein the reconfigurable logic is a memory.

10. The non-transitory computer-readable storage medium of claim 7 , wherein the pre-determined threshold is a maximum time allowed before a particular executable transaction must be executed.

11. The non-transitory computer-readable storage medium of claim 7 , wherein the second configuration is selected based on a length of a configuration queue associated with the second configuration.

12. The non-transitory computer-readable storage medium of claim 11 , wherein the second configuration is selected in response to being associated with the longest configuration queue.

13. A multicore processor system comprising:

a multicore processor comprising a plurality of processor elements, where at least one processor element comprises reconfigurable logic;

a plurality of executable transaction schedulers, each executable transaction scheduler comprising a scheduling algorithm for determining a most eligible executable transaction for execution from a number of candidate executable transactions, the plurality of executable transaction schedulers linked together to form a multilevel scheduler, the multilevel scheduler configured to output a most eligible executable transaction;

a configuration queue of executable transactions for a first configuration of the reconfigurable logic, the executable transactions allocated to and ready for execution by the reconfigurable logic, the configuration queue configured to receive the most eligible executable transaction and to output the most eligible executable transaction to the reconfigurable processor element for execution when the reconfigurable logic is configured according to the first configuration; and

a controller configured to reconfigure the reconfigurable logic according to a second configuration when a pre-determined threshold is reached.

14. The multicore processor system of claim 13 , wherein the controller is configured to:

stop the output of executable transactions from the configuration queue associated with the first configuration;

reconfigure the reconfigurable logic according to the second configuration;

provide a second configuration queue of executable transactions for the second configuration, the executable transactions of the second configuration queue allocated to and ready for execution by the reconfigurable logic; and

output the executable transactions of the second configuration queue to the reconfigurable processor element for execution.

15. The multicore processor system of claim 14 , wherein the reconfigurable logic is a memory.

16. The multicore processor system of claim 14 , wherein the pre-determined threshold is a maximum time allowed before a particular executable transaction must be executed.

17. The multicore processor system of claim 14 , wherein the second configuration is selected based on a length of a configuration queue associated with the second configuration.