Methods for fabricating transistors including one or more circular trenches
A transistor and a method of fabricating a transistor, including a metal oxide deposited on an epitaxial layer, a photo resist deposited and patterned over the metal oxide and the metal oxide and epitaxial layer are etched to form at least one circular trench, wherein the trench surfaces are defined by the epitaxial layer. An oxide layer is grown on the trench surfaces of each trench, and a gate conductor is formed within the at least one trench.
1. A transistor, comprising:
an epitaxial layer; and
a plurality of trenches, each trench comprising:
a circular cross-section,
a trench surface defined by the epitaxial layer,
a gate oxide disposed over the entire trench surface, and
a gate conductor deposited within the trench.
2. The transistor of claim 1 , further comprising P-type dopants implanted in the epitaxial layer forming a P+ contact.
3. The transistor of claim 2 , wherein:
the gate conductors deposited within the plurality of trenches comprise at least four gate conductors surrounding the P+ contact.
4. The transistor of claim 1 , further comprising:
a P-well surrounding at least one trench of the plurality of trenches, wherein the P-well is embedded into the epitaxial layer beneath the surface of the epitaxial layer; and
an N+ layer comprising N+ type dopants implanted in the epitaxial layer between the P-well and the surface of the epitaxial layer.
5. The transistor of claim 1 , wherein the epitaxial layer is disposed on an N+ doped substrate and the transistor is a metal oxide semiconductor field effect transistor (MOSFET).
6. The transistor of claim 1 , wherein the epitaxial layer is disposed on a P+ doped substrate and the transistor is an insulated gate bipolar transistor (IGBT).
7. The transistor of claim 1 , wherein the gate conductor comprises a compound selected from the group consisting of GaN, SiC, Si, and Ge.
8. A power conversion system comprising at least one switch, wherein the switch comprises a transistor including an epitaxial layer and a plurality of trenches, each trench comprising:
a circular cross-section,
a trench surface defined by the epitaxial layer,
a gate oxide disposed over the entire trench surface, and
a gate conductor deposited within the trench.
9. The power conversion system of claim 8 , wherein the transistor further includes P-type dopants implanted in the epitaxial layer forming a P+ contact.
10. The power conversion system of claim 9 , wherein:
the gate conductors deposited within the plurality of trenches surround the P+ contact; and
the ratio of the gate conductors to the P+ contact is in the range of 1:1 to 6:1.
11. The power conversion system of claim 8 , wherein:
the transistor further includes a P-well surrounding at least one trench of the plurality of trenches;
the P-well is embedded into the epitaxial layer beneath the surface of the epitaxial layer; and
the transistor further includes an N+ layer comprising N+ type dopants implanted in the epitaxial layer between the P-well and the surface of the epitaxial layer.
12. The power conversion system of claim 8 , wherein the epitaxial layer is disposed on an N+ doped substrate and the transistor is a metal oxide semiconductor field effect transistor (MOSFET).
13. The power conversion system of claim 8 , wherein the epitaxial layer is disposed on a P+ doped substrate and the transistor is an insulated gate bipolar transistor (IGBT).
14. A method of fabricating a transistor, comprising:
growing an epitaxial layer on a substrate;
depositing a first oxide layer on the epitaxial layer;
coating a photo resist over the first oxide layer and patterning the photo resist;
etching the first oxide layer and epitaxial layer to form a plurality of trenches, each trench having a circular cross-section and having a trench surface defined by the epitaxial layer;
growing a second oxide layer on the entire trench surfaces of the plurality of trenches;
forming a gate conductor within each trench.
15. The method of claim 14 , further comprising:
forming a P-well in the epitaxial layer; and
forming an N+ layer in the epitaxial layer between the P-well and the surface of the epitaxial layer surface.
16. The method of claim 14 , further comprising:
implanting P-type dopants in the epitaxial layer to form at least one P+ contact.
17. The transistor of claim 1 , further comprising:
a P-well implanted in the epitaxial layer; and
a plurality of P+ contacts implanted in the P-well, wherein:
the plurality of P+ contacts are electrically connected together, and
each P+ contact is surrounded by at least one trench of the plurality of trenches.
18. The transistor of claim 17 , wherein the gate conductors are electrically connected to a gate pad, and wherein the P+ contacts are electrically connected to a source pad.
19. The transistor of claim 1 , wherein a bottom surface of the gate conductor physically contacts an entire upper surface of the gate oxide.
20. The transistor of claim 1 , wherein an upper surface of the gate conductor in each trench has an extension that extends to and electrically connects the gate conductor in an adjacent trench.
21. The transistor of claim 1 , wherein the gate conductors deposited within the plurality of trenches are electrically connected together.
22. The power conversion system of claim 8 , wherein the gate conductors deposited within the plurality of trenches are electrically connected together.
23. The method of claim 14 , further comprising:
electrically connecting the gate conductors deposited within the plurality of trenches together.