Method for creating monocrystalline piezoresistors
An electrically insulating sheathing for a piezoresistor and a semiconductor material are provided such that the piezoresistor is able to be used in the high temperature range, e.g., for measurements at higher ambient temperatures than 200° C. A doped resistance area is initially laterally delineated by at least one circumferential essentially vertical trench and is undercut by etching over the entire area. An electrically insulating layer is then created on the wall of the trench and the undercut area, so that the resistance area is electrically insulated from the adjacent semiconductor material by the electrically insulating layer.
1. A method for creating a piezoresistor in the surface of a semiconductor substrate, comprising:
introducing at least one dopant into a selected surface area in the substrate to form a resistance area;
undercutting the resistance area by etching such that the resistance area is laterally delineated by a circumferential, essentially vertical trench; and
providing an electrically insulating layer on the resistance area, the wall and the base of the trench, such that the resistance area is electrically insulated from the adjacent semiconductor substrate material by the electrically insulating layer.
2. The method as recited in claim 1 , wherein the circumferential trench is isotropically widened in a base area of the trench, such that at least a base portion of the resistance area is undercut by etching.
3. The method as recited in claim 2 , wherein additional multiple trenches having a greater depth than the resistance area are provided within the resistance area, and wherein the additional multiple trenches are isotropically widened in the base area of the additional multiple trenches so that the resistance area is undercut by etching.
4. The method as recited in claim 1 , wherein:
the surface of the semiconductor substrate is provided with a trench mask having multiple perforations in a perforation area;
the vertical trench is formed by etching via the perforations; and
a distance between, and a size of, the multiple perforation openings are selected in such a way that the substrate, underneath the perforation area of the trench mask, is completely undercut by etching via the perforations.
5. The method as recited in claim 4 , wherein the trench mask includes a structured oxide layer.
6. The method as recited in claim 1 , wherein the electrically insulating layer is an oxide layer.
7. The method as recited in claim 4 , wherein, subsequent to etching of the vertical trench, the vertical trench is at least partially filled to form a closed planar surface.
8. The method as recited in claim 6 , wherein the electrically insulating layer further includes a polysilicon layer applied to the oxide layer, and wherein the polysilicon layer is oxidized.
9. The method as recited in claim 8 , wherein the resistance area is electrically contacted with the aid of multiple metal contacts from the top.
10. The method as recited in claim 9 , wherein two metal contacts are situated on two opposing end sections of the resistance area, and wherein the two opposing end sections of the resistance area are wider than the central area of the resistance area.
11. The method as recited in claim 1 , further comprising:
providing the piezoresistor in a micromechanical component that further includes at least one bendable structure element, wherein the piezoresistor is configured as a monocrystalline piezoresistor for signal detection.
12. The method as recited in claim 1 , wherein:
the circumferential trench is at an edge of the resistance area;
the undercutting further includes:
etching a plurality of trench openings within the resistance area;
isotropically widening a base area of the circumferential trench for undercutting at least an outer edge region of the resistance area; and
isotropically widening a base area of the trench openings; and
the trench openings are deeper than portions of the resistance area undercut by the undercutting step.
13. The method as recited in claim 6 , wherein the oxide layer is produced by thermal oxidation.
14. The method as recited in claim 6 , wherein the oxide layer is produced by deposition.
15. A method for creating a piezoresistor in a surface of a semiconductor substrate, comprising:
introducing at least one dopant into a selected surface area in the substrate to form a resistance area;
etching a circumferential trench at an edge of a resistance area;
etching a plurality of trenches within the resistance area;
isotropically widening a base area of the circumferential trench, thereby undercutting at least an outer edge region of the resistance area;
isotropically widening respective base areas of respective ones of the plurality of trenches, thereby undercutting respective portions of the resistance area that are adjacent respective ones of the plurality of trenches, wherein the plurality of trenches are deeper than the respective portions of the resistance area they undercut; and
providing an electrically insulating layer on the resistance area, the wall of the circumferential trench, and the base of the circumferential trench, the resistance area thereby being electrically insulated from adjacent semiconductor substrate material.
16. The method as recited in claim 15 , wherein the circumferential trench extends around a perimeter of the resistance area and the plurality of trenches.
17. The method as recited in claim 16 , wherein the electrically insulating material is also provided on the bases and walls of the plurality of trenches.
18. The method as recited in claim 15 , wherein the electrically insulating material is also provided on the bases and walls of the plurality of trenches.