Restart index that sets a topology
One embodiment of the present invention sets forth a technique for reducing overhead associated with transmitting primitive draw commands from memory to a graphics processing unit (GPU). Command pairs comprising an end draw command and a begin draw command associated with a conventional graphics application programming interface (API) are selectively replaced with a new construct. The new construct is a reset topology index, which implements a combined function of the end draw command and begin draw command. The new construct improves efficiency by reducing total data transmitted from memory to the GPU.
1. A computer-implemented method for generating an index sequence, the method comprising:
receiving a topology element via an application programming interface (API) that includes a draw command defining a topology to be drawn, and a set of vertex indices for the topology that refer to vertex data residing in a vertex buffer;
instantiating a reset topology index within an index buffer, wherein the reset topology index includes a topology descriptor for the topology; and
instantiating the set of vertex indices within the index buffer,
wherein a combination of the reset topology index and the set of vertex indices forms the index sequence, and
wherein the index sequence is transmitted to a processing unit for processing plural draw commands for different types of topologies using one index sequence.
2. The method of claim 1 , wherein the received topology element comprises a begin command.
3. The method of claim 1 , wherein the index sequence is between a begin command and an end command.
4. The method of claim 1 , wherein the reset topology index comprises a constant pattern that defines the reset topology index.
5. The method of claim 4 , wherein the constant pattern comprises a sequence of ones in a set of most significant bit positions.
6. The method of claim 5 , wherein the topology descriptor comprises bits from a set of least significant bit positions.
7. The method of claim 5 , wherein the reset topology index comprises sixteen bits, and the topology descriptor comprises four least significant bits.
8. The method of claim 1 , wherein the vertex buffer and index buffer reside in a system memory.
9. The method of claim 8 , wherein the vertex buffer is located within the system memory via a first buffer pointer, and the index buffer is located within the system memory via a second buffer pointer.
10. A computer-implemented method for interpreting an index sequence to render a topology, the method comprising:
receiving data from the index sequence that includes a first index that is associated with the index sequence and defines at least in part a first topology;
determining that the first index comprises a reset topology index based on at least a portion of the first index matching a constant pattern;
changing a current topology to the first topology based on a topology descriptor extracted from the first index, wherein the current topology is different than the first topology;
accumulating a plurality of vertices included within the first topology; and
processing the plurality of vertices to render the first topology.
11. The method of claim 10 , wherein the reset topology index comprises a constant pattern that defines the reset topology index.
12. The method of claim 11 , wherein the constant pattern comprises a sequence of ones in a set of most significant bit positions.
13. The method of claim 12 , wherein the topology descriptor comprises bits from a set of least significant bit positions.
14. The method of claim 12 , wherein the reset topology index comprises sixteen bits and the topology descriptor comprises four least significant bits.
15. The method of claim 10 , wherein the vertex buffer and index buffer reside in a system memory.
16. The method of claim 15 , wherein the vertex buffer is located within the system memory via a first buffer pointer, and the index buffer is located within the system memory via a second buffer pointer.
17. The method of claim 10 , wherein the step of accumulating further comprises the step of adding the current index to the first topology.
18. A computer system, comprising:
a system memory;
a first processing unit coupled to the system memory and configured to:
receive a topology element via an application programming interface (API) that includes a draw command defining a topology to be drawn, a set of vertex indices for the topology that refer to vertex data residing in a vertex buffer, and an end draw command;
instantiate a reset topology index within an index buffer, wherein the reset topology index includes a topology descriptor for the topology; and
instantiate the set of vertex indices within the index buffer,
wherein a combination of the reset topology index and the set of vertex indices forms the index sequence, and
wherein the index sequence is transmitted to a processing unit for processing plural draw commands for different types of topologies using one index sequence;
a second processing unit coupled to the system memory and configured to:
receive data from the index sequence that includes a first index that is associated with the index sequence and defines at least in part a first topology;
determine that the first index comprises a reset topology index based on at least a portion of the first index matching a constant pattern;
change a current topology to the first topology based on a topology descriptor extracted from the first index;
accumulate a plurality of vertices included within the first topology; and
process the plurality of vertices to render the first topology.
19. The system of claim 18 , wherein the received topology element comprises a begin command.
20. The system of claim 18 , wherein the index sequence is between a begin command and an end command.
21. The system of claim 18 , wherein the reset topology index comprises a constant pattern that defines the reset topology index.
22. The system of claim 21 , wherein the reset topology index comprises sixteen bits, the constant pattern comprises a string of ones in the twelve most significant bits, and the topology descriptor comprises four least significant bits.
23. The system of claim 18 , wherein the vertex buffer and index buffer reside in the system memory.
24. The system of claim 18 , wherein the vertex buffer is located within the system memory via a first buffer pointer, and the index buffer is located within the system memory via a second buffer pointer.