IP Library Granted Patent US 8,780,124
Granted Patent B2
US 8,780,124 · App. 13/170,404 · Granted Jul 15, 2014

Graphic processing apparatus and computer-readable medium storing graphic processing program

Inventor: Hidefumi Nishi (Yokohama, JP)
Assignee: Fujitsu Semiconductor Limited
G06G5/363
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,780,124
App. No.
13/170,404
Granted
Jul 15, 2014
Kind
B2
Abstract

A graphic processing apparatus includes a chunk assignment unit which assigns a block in which a maximum N number of polygons are located, out of a plurality of polygons drawn in a frame buffer which is divided into a plurality of blocks, to a maximum M number of chunk buffers; a chunk generation unit which generates pixel data of a polygon located in a block assigned to the chunk buffer, out of the N number of polygons, and writes the pixel data to the chunk buffer; and a chunk writing unit which writes the pixel data written in the chunk buffer to the frame buffer, wherein a processing phase, including processing by the chunk assignment unit, processing by the chunk generation unit, and processing by the chunk writing unit, is repeatedly executed for the plurality of polygons.

Claims (47)

1. A graphic processing apparatus which draws pixel data of a plurality of polygons in a frame buffer having a plurality of blocks being divided, comprising:

a plurality of chunk buffers each configured to being same size as the block;

a chunk assignment unit configured to perform assigning the blocks, in which a target polygon being processed is located, to the plurality of chunk buffers sequentially, until the number of assigned chunk buffers reaches M units, a shape of the plurality of assigned blocks becomes non-rectangular in accordance with the target polygon when the target polygon is located in the plurality of adjacent blocks;

a chunk generation unit configured to generate pixel data of the target polygons, the pixel data being located in the blocks assigned to the plurality of chunk buffers, and writes the pixel data to the plurality of chunk buffers; and

a chunk writing unit configured to write the pixel data written in the plurality of chunk buffers to the frame buffer, wherein

a processing phase, including processing of the assigning by the chunk assignment unit, processing of generating and writing pixel data by the chunk generation unit, and processing of writing pixel data to the frame buffer by the chunk writing unit, is repeatedly executed for the plurality of polygons.

2. The graphic processing apparatus according to claim 1 , wherein

the chunk generation unit reads the pixel data of the block assigned to the plurality of chunk buffers from the frame buffer, and writes the pixel data to the plurality of chunk buffers in each processing phase, and writes the generated pixel data to the plurality of chunk buffers where the read pixel data have been written.

3. The graphic processing apparatus according to claim 2 , wherein

the graphic processing apparatus further comprises a polygon parameter buffer generation unit which generates drawing parameters based on vertex data of the polygons, and writes the drawing parameters to the polygon parameter buffer in each processing phase, and

the chunk generation unit generates pixel data of the polygons based on the drawing parameters of the polygon parameter buffer.

4. The graphic processing apparatus according to claim 3 , wherein

in a first processing phase, the polygon parameter buffer generation unit keeps the drawing parameters of a polygon for which the generation of the pixel data is not completed, out of the drawing parameters of the polygons written in the polygon parameter buffer, in the polygon parameter buffer in the second processing phase which comes after the first processing phase, and the polygon parameter buffer generation unit generates drawing parameters of the polygons, along with the polygon of which drawing parameters have been kept, and writes the drawing parameters in the polygon parameter buffer.

5. The graphic processing apparatus according to claim 3 , wherein

the pixel data further has a depth value which indicates depth, and

when the depth value of the generated pixel data is smaller than a depth value of a corresponding pixel of the pixel data read from the frame buffer, the chunk generation unit writes the generated pixel data to the plurality of chunk buffers.

6. The graphic processing apparatus according to claim 5 , wherein

the drawing parameters of the polygon parameter buffer are stored in association with the identification information, and

the chunk generation unit stores, for each pixel of the block, the identification information in the polygon parameter buffer associated with a polygon having the smallest depth value, out of the polygons located in the block, to the polygon parameter indication buffer, and generates pixel data of the polygons by referring to the drawing parameters based on the identification information in the polygon parameter indication buffer.

7. The graphic processing apparatus according to claim 4 , wherein

for a polygon of which generation of the pixel data is not completed, the chunk assignment unit writes coordinate information, which indicates a pixel for which this generation is not completed, to the polygon parameter buffer in the first phase, and

for the polygon for which generation of the pixel data is not completed, the chunk assignment unit assigns the block, where the pixel indicated by the coordinate information in the polygon parameter buffer is located, to the chunk buffer in the second phase.

8. The graphic processing apparatus according to claim 1 , wherein

an access speed is faster in the chunk buffer than in the frame buffer.

9. The graphic processing apparatus according to claim 3 , wherein

an access speed is faster in the polygon parameter buffer than in the frame buffer.

10. A non-transitory computer-readable medium storing a graphic processing program for draw pixel data of a plurality of polygons in a frame buffer having a plurality of blocks being divided, the program causes a computer repeatedly to execute a process comprising:

a chunk assigning which performs assigning the blocks, in which a target polygon being processed is located, to a plurality of chunk buffers sequentially, until the number of assigned chunk buffers reaches M units, a shape of the plurality of assigned blocks becomes non-rectangular in accordance with the target polygon when the target polygon is located in the plurality of adjacent blocks;

a chunk generating which generates pixel data of the target polygons, the pixel data being located in the blocks assigned to the plurality of chunk buffers, and writes the pixel data to the plurality of chunk buffers; and

a chunk writing which writes the pixel data written in the plurality of chunk buffers to the frame buffer.

11. The graphic processing program according to claim 10 , wherein

the chunk generating includes reading the pixel data of the block assigned to the plurality of chunk buffers from the frame buffer, writing the pixel data to the plurality of chunk buffers in each processing phase, and writing the generated pixel data to the plurality of chunk buffers where the read pixel data have been written.

12. The graphic processing program according to claim 11 , further comprising a polygon parameter buffer generating drawing parameters based on vertex data of the polygons and writing the drawing parameters to the polygon parameter buffer in each processing phase, wherein

the chunk generating includes generating pixel data of the polygons based on the drawing parameters of the polygon parameter buffer.

13. The graphic processing program according to claim 12 , wherein

in a first processing phase, the polygon parameter buffer generating includes keeping the drawing parameters of a polygon for which generation of the pixel data is not completed, out of the drawing parameters of the polygons written in the polygon parameter buffer in a second processing phase which comes after the first processing phase, and the polygon parameter buffer generating includes generating drawing parameters of the polygons, along with the polygon of which drawing parameters have been kept, and writing the drawing parameters in the polygon parameter buffer.

14. The graphic processing program according to claim 13 , wherein

for a polygon for which generation of the pixel data is not completed, the chunk assigning includes writing coordinate information, which indicates a pixel of which this generation is not completed, to the polygon parameter buffer in the first phase, and

for the polygon of which generation of the pixel data is not completed, the chunk assigning includes assigning the block, where the pixel indicated by the coordinate information in the polygon parameter buffer is located, to the chunk buffer in the second phase.

15. The graphic processing apparatus according to claim 1 , wherein

the chunk assignment unit repeats the assigning until the number of the target polygons reaches N units.

16. The graphic processing apparatus according to claim 1 , wherein

the chunk assignment unit detects the coordinate in the frame buffer which the target polygon is drawn sequentially, and assigns the block which corresponding to the coordinate, to the chunk buffer.

17. The graphic processing apparatus according to claim 1 , wherein

the chunk assigning repeats the assigning until the number of the target polygons reaches N units.

18. The graphic processing apparatus according to claim 1 , wherein

the chunk assigning detects the coordinate in the frame buffer which the target polygon is drawn sequentially, and assigns the block which corresponding to the coordinate, to the chunk buffer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2011
From: NISHI, HIDEFUMI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 026611/0135 →
Priority Claims (1)
JP 2010-206860 · Sep 15, 2010 · national
Continuity (1)
Related Publication 20120062578A1 · Mar 15, 2012