Interface between multiple controllers
A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface.
1. A method, comprising:
communicating with a second controller from a first controller via an interface; and
communicating with storage from the first controller via the interface, wherein:
the first controller is configured to be a master on the interface;
the second controller and the storage are configured to be targets on the interface;
the second controller is configured to be in a first write mode, wherein in response to receiving a write instruction, the second controller is configured to:
determine whether a write address associated with the write instruction is within a range of predefined addresses; and
in the event it is determined that the write address is within the range of predefined addresses, store data associated with the write instruction in a second storage managed by the second controller even if a chip select signal associated with the interface indicates that the second controller is not selected; and
the storage is configured to be in a second write mode, wherein in response to receiving the same write instruction as the second controller, the storage is configured to:
determine whether the chip select signal indicates that the storage is selected; and
in the event it is determined that the chip select signal indicates that the storage is selected, store the data associated with the write instruction in the storage, such that in the event (1) the write address is within the range of predefined addresses and (2) the chip select signal indicates that the storage is selected, the data associated with the write instruction is stored in both the storage and the second storage.
2. The method recited in claim 1 , wherein the interface includes a double data rate (DDR) interface.
3. The method recited in claim 1 , wherein the first controller includes one or more of the following: a microprocessor, an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
4. The method recited in claim 1 , wherein the first controller is a first semiconductor component on a printed circuit board (PCB), the second controller is a second semiconductor component on the PCB and the storage is a third semiconductor component on the printed circuit board.
5. The method recited in claim 1 , wherein the storage includes a dynamic random-access memory (DRAM).
6. The method recited in claim 1 , wherein the first controller includes a first storage controller configured to manage magnetic disk storage and the second controller includes a second storage controller configured to manage Flash memory.
7. The method recited in claim 1 , wherein:
either the storage or the second controller is located further away from the first controller than the other component; and
the further-away component includes an on-die termination (ODT) on a connection associated with the interface.
8. The method recited in claim 7 further comprising turning on the ODT during one or more of the following: a write operation or a read operation.
9. The method recited in claim 7 , wherein the ODT is on one or more of the following: an address connection associated with the interface, a control connection associated with the interface or a chip select connection associated with the interface.
10. The method recited in claim 1 , wherein the first controller includes an on-die termination (ODT) on a data connection associated with the interface.
11. The method recited in claim 10 further comprising turning on the ODT during a read operation.
12. The method recited in claim 1 , wherein:
the storage includes an on-die termination (ODT) on a data connection associated with the interface; and
the method further includes keeping the ODT turned off at all times.
13. A system, comprising:
a first controller configured to be a master on an interface;
a second controller; and
a storage, wherein:
the second controller and the storage are configured to be targets on the interface;
from the first controller, the second controller is communicated with via the interface;
the second controller is configured to be in a first write mode, wherein in response to receiving a write instruction, the second controller is configured to:
determine whether a write address associated with the write instruction is within a range of predefined addresses; and
in the event it is determined that the write address is within the range of predefined addresses, store data associated with the write instruction in a second storage managed by the second controller even if a chip select signal associated with the interface indicates that the second controller is not selected; and
the storage is configured to be in a second write mode, wherein in response to receiving the same write instruction as the second controller, the storage is configured to:
determine whether the chip select signal indicates that the storage is selected; and
in the event it is determined that the chip select signal indicates that the storage is selected, store the data associated with the write instruction in the storage, such that in the event (1) the write address is within the range of predefined addresses and (2) the chip select signal indicates that the storage is selected, the data associated with the write instruction is stored in both the storage and the second storage.
14. The system recited in claim 13 , wherein the first controller includes one or more of the following: a microprocessor, an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
15. The system recited in claim 13 , wherein the first controller is a first semiconductor component on a printed circuit board (PCB), the second controller is a second semiconductor component on the PCB and the storage is a third semiconductor component on the printed circuit board.
16. The system recited in claim 13 , wherein the first controller includes a first storage controller configured to manage magnetic disk storage and the second controller includes a second storage controller configured to manage Flash memory.
17. The system recited in claim 13 , wherein:
either the storage or the second controller is located further away from the first controller than the other component; and
the further-away component includes an on-die termination (ODT) on a connection associated with the interface.
18. The system recited in claim 13 , wherein the first controller includes an on-die termination (ODT) on a data connection associated with the interface.