Loop parallelization based on loop splitting or index array

1. A method executed by a processor, the method comprising:

identifying a loop for speculative parallelization based on control and data dependence information;

generating one or more speculation guards to preserve speculation information, corresponding to the loop, in response to a determination that the loop is to be parallelized;

determining mis-speculation information for both control and data speculation based on execution of an inspection code, wherein the inspection code is to be generated based on the one or more speculation guards; and

generating one or more split loops, corresponding to the loop, based on the mis-speculation information, wherein the loop is parallelized based on successful data speculation for every iteration of a dependence edge, carried by the loop, between a store operation which has a non-linear array subscript and a load operation which has a linear or a non-linear array subscript.

2. The method of claim 1 , further comprising analyzing optimization information to generate control and data dependence information.

3. The method of claim 2 , wherein the optimization information is to comprise one or more of heuristics or profiling information.

4. The method of claim 1 , further comprising determining whether to parallelize the loop, wherein determining whether to parallelize the loop is based on a determination of whether parallelizing the loop is to result in speed up.

5. The method of claim 1 , further comprising generating a placeholder for the loop.

6. The method of claim 5 , further comprising updating a control and data dependence graph corresponding of the placeholder.

7. The method of claim 6 , wherein updating the control and data dependence graph is to comprise eliminating one or more highly unlikely taken branches and ignoring low probability data dependence.

8. The method of claim 1 , further comprising applying analyses and transformations at a later phase of a compiler without change to accommodate the speculation information based on the one or more speculation guards, wherein the one or more speculation guards are to be generated at an earlier phase of the compiler.

9. The method of claim 1 , further comprising generating the inspection code based on the one or more speculation guards.

10. The method of claim 1 , wherein the one or more split loops are to comprise one or more of disjoint index set, fewer branches, or fewer loop carried dependences when compared to the loop.

11. A method executed by a processor, the method comprising:

storing in an index array a set of indices for which an if-condition of a loop is always true for only one iteration set; and

generating a plurality of subloops from the loop based on the index array, wherein the index array is to cause breaking of one or more control flow and data flow dependencies in the loop, wherein flow analysis for the set of indices is performed at compile time, while values of iteration subspaces, corresponding to the iteration set, are generated at runtime to break control and data flow dependences, wherein generating the plurality of subloops is performed in response to a determination that an if-condition with a single branch, such that a predicate of the if-condition depends on a loop index variable, being responsible for the one or more control flow dependences.

12. The method of claim 11 , further comprising reordering the plurality of the subloops based on the index array.

13. The method of claim 11 , wherein the index array is to comprise a subset of an iteration space of the loop constructed by selecting an iteration set in response to a flow or anti-flow dependency edge in the loop existing for only one iteration set.

14. The method of claim 11 , further comprising generating a subloop based on the loop by replacing one or more occurrences of an index variable by a corresponding index array element.

15. The method of claim 11 , further comprising generating two pre-computation loops for construction of the index array.

16. The method of claim 11 , further comprising converting the loop into a two-level loop nest.

17. A non-transitory computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:

identify a loop for speculative parallelization based on control and data dependence information;

generate one or more speculation guards to preserve speculation information, corresponding to the loop, in response to a determination that the loop is to be parallelized;

determine mis-speculation information for both control and data speculation based on execution of an inspection code, wherein the inspection code is to be generated based on the one or more speculation guards; and

generate one or more split loops, corresponding to the loop, based on the mis-speculation information, wherein the loop is parallelized based on successful data speculation for every iteration of a dependence edge, carried by the loop, between a store operation which has a non-linear array subscript and a load operation which has a linear or a non-linear array subscript.

18. The computer-readable medium of claim 17 , further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to analyze optimization information to generate control and data dependence information.

19. The computer-readable medium of claim 17 , further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to determine whether to parallelize the loop based on a determination of whether parallelizing the loop is to result in speed up.

20. The computer-readable medium of claim 17 , further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to generate a placeholder for the loop.

21. The computer-readable medium of claim 17 , further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to update a control and data dependence graph corresponding of the placeholder.

22. The computer-readable medium of claim 17 , further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to apply analyses and transformations at a later phase of a compiler without change to accommodate the speculation information based on the one or more speculation guards, wherein the one or more speculation guards are to be generated at an earlier phase of the compiler.

23. The computer-readable medium of claim 17 , further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to generate the inspection code based on the one or more speculation guards.

24. A non-transitory computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:

store in an index array a set of indices for which an if-condition of a loop is always true for only one iteration set; and

generate a plurality of subloops from the loop based on the index array, wherein the index array is to cause breaking of one or more control flow and data flow dependencies in the loop, wherein flow analysis for the set of indices is performed at compile time, while values of iteration subspaces, corresponding to the iteration set, are generated at runtime to break control and data flow dependences, wherein generating the plurality of subloops is to be performed in response to a determination that an if-condition with a single branch, such that a predicate of the if-condition depends on a loop index variable, being responsible for the one or more control flow dependences.

25. The computer-readable medium of claim 24 , further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to reorder the plurality of the subloops based on the index array.

26. The computer-readable medium of claim 24 , wherein the index array is to comprise a subset of an iteration space of the loop constructed by selecting an iteration set in response to a flow or anti-flow dependency edge in the loop existing for only one iteration set.

27. The computer-readable medium of claim 24 , further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to generate a subloop based on the loop by replacing one or more occurrences of an index variable by a corresponding index array element.

28. The computer-readable medium of claim 24 , further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to generate two pre-computation loops for construction of the index array.

29. The computer-readable medium of claim 24 , further comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to convert the loop into a two-level loop nest.