Group III-V device structure having a selectively reduced impurity concentration
There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.
1. A semiconductor structure comprising:
a substrate;
a transition body over said substrate;
a group III-V intermediate body having a bottom surface over said transition body;
a group III-V device layer over a top surface of said group III-V intermediate body;
said group III-V intermediate body having a continuously reduced impurity concentration wherein a higher impurity concentration at said bottom surface is continuously reduced to a lower impurity concentration at said top surface;
said lower impurity concentration occurring at a depth below said top surface and remaining substantially constant from said depth to said top surface.
2. The semiconductor structure of claim 1 , wherein an impurity producing said higher and lower impurity concentrations is a P type impurity.
3. The semiconductor structure of claim 1 , wherein said continuously reduced impurity concentration comprises a continuously reduced carbon concentration.
4. The semiconductor structure of claim 1 , wherein said continuously reduced impurity concentration includes a plurality of impurity species.
5. The semiconductor structure of claim 1 , wherein said group III-V intermediate body comprises a compositionally graded III-Nitride body having a first, III-Nitride composition at said bottom surface and a second III-Nitride composition above said bottom surface.
6. The semiconductor structure of claim 1 , wherein said group III-V device layer includes at least one of a III-Nitride field-effect transistor (FET) and a III-Nitride high electron mobility transistor (HEMT).
7. The semiconductor structure of claim 1 , wherein said transition body includes a group III-V transition structure having a selectively modified impurity concentration such that a bottom surface impurity concentration of said group III-V transition structure is selectively modified to a top surface impurity concentration of said group III-V transition structure.
8. The semiconductor structure of claim 7 , wherein said selectively modified impurity concentration is modified in a step-wise fashion from said bottom surface impurity concentration to said top surface impurity concentration.
9. A method comprising:
fabricating a transition body over a substrate;
fabricating a group III-V intermediate body having a bottom surface over said transition body;
fabricating a group III-V device layer over a top surface of said group III-V intermediate body;
wherein fabricating said group III-V intermediate body comprises forming a continuously reduced impurity concentration such that a higher impurity concentration at said bottom surface is continuously reduced to a lower impurity concentration at said top surface;
said lower impurity concentration occurring at a depth below said top surface and remaining substantially constant from said depth to said top surface.
10. The method of claim 9 , wherein fabricating said group III-V intermediate body comprises selectively reducing a growth rate of said group III-V intermediate body from a higher growth rate at said bottom surface to a lower growth rate at said top surface.
11. The method of claim 9 , wherein fabricating said group III-V intermediate body comprises selectively increasing a growth temperature of said group III-V intermediate body from a lower growth temperature at said bottom surface to a higher growth temperature at said top surface.
12. The method of claim 9 , wherein an impurity producing said higher and lower impurity concentrations is a P type impurity.
13. The method of claim 9 , wherein forming said continuously reduced impurity concentration comprises forming a continuously reduced carbon concentration.
14. The method of claim 9 , wherein said continuously reduced impurity concentration includes a plurality of impurity species.
15. The method of claim 9 , wherein said group III-V intermediate body comprises a compositionally graded III-Nitride body having a first III-Nitride composition at said bottom surface and a second III-Nitride composition above said bottom surface.
16. The method of claim 9 , wherein said group III-V device layer includes at least one of a III-Nitride field-effect transistor (FET) and a III-Nitride high electron mobility transistor (HEMT).
17. The method of claim 9 , wherein fabricating said transition body includes fabricating a group III-V transition structure having a selectively modified impurity concentration such that a bottom surface impurity concentration of said group III-V transition structure is selectively modified to a top surface impurity concentration of said group III-V transition structure.
18. The method of claim 17 , wherein said selectively modified impurity concentration is reduced in a step-wise fashion from said bottom surface impurity concentration to said top surface impurity concentration.