Scanning signal line drive circuit and display device having the same
Stability of a circuit operation in a monolithic gate driver is improved. A bistable circuit is provided with a charge replenishment circuit ( 71 ) including: a capacitor (CAP 2 ); a thin-film transistor (MA) having a first electrode supplied with a first clock for charge replenishment (CKA), a second electrode connected to a third-node (N 3 ) connected to one end of the capacitor (CAP 2 ), and a third electrode connected to a second-node (N 2 ) to be maintained at the high level during a normal operation period; and a thin-film transistor (MB) having a first electrode supplied with a second clock for charge replenishment (CKB), a second electrode supplied with a high-level DC power supply potential (VDD), and a third electrode connected to the third-node (N 3 ). The first clock for charge replenishment (CKA) and the second clock for charge replenishment (CKB) are alternately driven to the high level so as to eliminate a period in which “the first clock for charge replenishment (CKA) is at the high level and the second clock for charge replenishment (CKB) is at the high level”.
1. A scanning signal line drive circuit of a display device, that drives a plurality of scanning signal lines which are arrayed in a display unit, the circuit comprising:
a shift register having a plurality of bistable circuits connected in series with each other, outputted signals from the plurality of bistable circuits being sequentially driven active based on a plurality of clock signals that are externally inputted and cyclically repeat a first level and a second level, wherein
each bistable circuit includes:
a first-input-node configured to receive an outputted signal from a bistable circuit of a stage before the each bistable circuit as a set signal;
a first-output-node connected to the scanning signal line and configured to output an outputted signal from the each bistable circuit as a scanning signal for driving the scanning signal line;
a first output control switching element having a second electrode supplied with one of the plurality of clock signals as a first clock for operation control and a third electrode connected to the first-output-node;
a first-node turnon switching element configured to change a level of a first-node to an ON level based on the set signal, the first-node being connected to a first electrode of the first output control switching element;
at least one of a first first-node turnoff switching element and a first first-output-node turnoff switching element, the first first-node turnoff switching element having a second electrode connected to the first-node and being configured to change the level of the first-node to an OFF level, the first first-output-node turnoff switching element having a second electrode connected to the first-output-node, having a third electrode supplied with an OFF level potential, and being configured to change a level of the first-output-node to the OFF level;
a second-node turnoff switching element having a second electrode connected to a second-node, having a third electrode supplied with an OFF level potential, and configured to turn the second-node to the OFF level during a period in which the first-node is to be maintained at the ON level, the second-node being connected to a first electrode of at least one of the first first-node turnoff switching element and the first first-output-node turnoff switching element;
a first charge replenishment switching element having a first electrode supplied with one of the plurality of clock signals as a first clock for charge replenishment and having a third electrode connected to the second-node;
a capacitative element having one end connected to a third-node connected to a second electrode of the first charge replenishment switching element; and
a second charge replenishment switching element having a third electrode connected to the third-node, having a first electrode supplied with one of the plurality of clock signals as a second clock for charge replenishment, and configured to charge the capacitative element based on the second clock for charge replenishment,
the first charge replenishment switching element is turned to an ON state when the first clock for charge replenishment is at the first level,
the second charge replenishment switching element is turned to an ON state when the second clock for charge replenishment is at the first level, and
when the first clock for charge replenishment is at the first level, the second clock for charge replenishment is at the second level.
2. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit includes, as the second-node turnoff switching element:
a first second-node turnoff switching element having a first electrode connected to the first-input-node, a second electrode connected to the second-node, and a third electrode supplied with an OFF level potential; and
a second second-node turnoff switching element having a first electrode connected to the first-output-node, a second electrode connected to the second-node, and a third electrode supplied with an OFF level potential.
3. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit includes, as the second-node turnoff switching element, a third second-node turnoff switching element having a first electrode connected to the first-node, a second electrode connected to the second-node, and a third electrode supplied with an OFF level potential.
4. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit further includes:
a second-input-node configured to receive an outputted signal from a bistable circuit of a stage after the each bistable circuit as a reset signal; and
a first second-node turnon switching element configured to change a level of the second-node to the ON level based on the reset signal.
5. The scanning signal line drive circuit according to claim 1 , wherein
in each bistable circuit, a potential of the second-node is maintained at a substantially constant potential based on a high-level DC power supply potential during a period in which the first-node is to be maintained at the OFF level.
6. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit includes the first first-node turnoff switching element, and
a third electrode of the first first-node turnoff switching element is connected to the first-output-node.
7. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit further includes:
a second-input-node configured to receive an outputted signal from a bistable circuit of a stage after the each bistable circuit as a reset signal; and
a second first-output-node turnoff switching element having a first electrode connected to the second-input-node, a second electrode connected to the first-output-node, and a third electrode supplied with an OFF level potential.
8. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit further includes:
a second-input-node configured to receive an outputted signal from a bistable circuit of a stage after the each bistable circuit as a reset signal; and
a second first-node turnoff switching element having a first electrode connected to the second-input-node, a second electrode connected to the first-node, and a third electrode supplied with an OFF level potential.
9. The scanning signal line drive circuit according to claim 1 , wherein
the first-node turnon switching element is a thin-film transistor having a multichannel structure.
10. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit includes the first first-node turnoff switching element, and
the first first-node turnoff switching element is a thin-film transistor having a multichannel structure.
11. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit further includes:
a second-input-node configured to receive an outputted signal from a bistable circuit of a stage after the each bistable circuit as a reset signal;
a second-output-node configured to output an outputted signal from the each bistable circuit as a different stage control signal for controlling an operation of a bistable circuit other than the each bistable circuit; and
a second output control switching element having a first electrode connected to the first-node, a second electrode connected to the second electrode of the first output control switching element, and a third electrode connected to the second-output-node, wherein
the different stage control signal outputted from each bistable circuit is supplied to a bistable circuit of a stage before the each bistable circuit as the reset signal.
12. The scanning signal line drive circuit according to claim 11 , wherein
each bistable circuit further includes:
a second-input-node configured to receive an outputted signal from a bistable circuit of a stage after the each bistable circuit as a reset signal; and
a first second-node turnon switching element configured to change a level of the second-node to the ON level based on the reset signal, wherein
a second electrode of the first second-node turnon switching element is supplied with one of the plurality of clock signals that is different from a signal supplied to the second electrode of the first output control switching element.
13. The scanning signal line drive circuit according to claim 11 , wherein
the second electrode of the first output control switching element is supplied with a DC power supply potential in place of one of the plurality of clock signals.
14. The scanning signal line drive circuit according to claim 13 , wherein
the following expression is satisfied, where an amplitude voltage of the plurality of clock signals is VCK, and a voltage of the scanning signal when the scanning signal line is driven taking a potential on a low level side of the plurality of clock signals as a reference is VGH
VGH≧VCK≧VGH/ 2.
15. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit further includes:
a second-output-node configured to output an outputted signal from the each bistable circuit as a different stage control signal for controlling an operation of a bistable circuit other than the each bistable circuit; and
a second output control switching element having a first electrode connected to the first-node, a second electrode connected to the second electrode of the first output control switching element, and a third electrode connected to the second-output-node, wherein
the different stage control signal outputted from each bistable circuit is supplied to a bistable circuit of a stage after the each bistable circuit as the set signal.
16. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit further includes:
a third-input-node configured to receive a signal externally supplied as a clear signal; and
a second second-node turnon switching element configured to change a level of the second-node to the ON level based on the clear signal.
17. The scanning signal line drive circuit according to claim 16 , wherein
each bistable circuit further includes:
a second-input-node configured to receive an outputted signal from a bistable circuit of a stage after the each bistable circuit as a reset signal; and
a first second-node turnon switching element configured to change the level of the second-node to the ON level based on the reset signal, wherein
a last stage bistable circuit out of the plurality of bistable circuits is supplied with the clear signal as the reset signal.
18. The scanning signal line drive circuit according to claim 16 , wherein
each bistable circuit further includes:
a fourth-input-node configured to receive a signal externally supplied as a refresh signal; and
a second-node level lowering switching element configured to change the level of the second-node to a level lower than the OFF level based on the refresh signal.
19. The scanning signal line drive circuit according to claim 1 , wherein
each bistable circuit further includes:
a third-input-node configured to receive a signal externally supplied as a clear signal;
a second second-node turnon switching element configured to change a level of the second-node to the ON level based on the clear signal; and
a second-node level lowering switching element configured to change the level of the second-node to a level lower than the OFF level based on the clear signal.
20. The scanning signal line drive circuit according to claim 1 , wherein
depending on the clock signal inputted to each bistable circuit as the first clock for operation control, the clock signal inputted to the each bistable circuit as the first clock for charge replenishment and the clock signal inputted to the each bistable circuit as the second clock for charge replenishment are determined.
21. The scanning signal line drive circuit according to claim 20 , wherein
the clock signal inputted to each bistable circuit as the first clock for operation control is inputted to the each bistable circuit as the second clock for charge replenishment, and a clock signal out of phase with the first clock for operation control by 180 degrees is inputted to the each bistable circuit as the first clock for charge replenishment.
22. The scanning signal line drive circuit according to claim 1 , wherein
the plurality of bistable circuits are configured by a plurality of bistable-circuit pairs connected in series with each other, each bistable-circuit pair being constituted by two consecutive stages of bistable circuits, and
in the bistable-circuit pair,
the second electrode of the first charge replenishment switching element included in the bistable circuit of a previous stage is connected to the second electrode of the first charge replenishment switching element in the bistable circuit of a next stage,
the capacitative element and the second charge replenishment switching element are shared between the previous stage bistable circuit and the next stage bistable circuit.
23. The scanning signal line drive circuit according to claim 22 , wherein
the previous stage bistable circuit in the bistable-circuit pair includes, as the second-node turnoff switching element, a first second-node turnoff switching element having a first electrode connected to the first-input-node, a second electrode connected to the second-node, and a third electrode supplied with an OFF level potential,
the next stage bistable circuit in the bistable-circuit pair includes, as the second-node turnoff switching element, a second second-node turnoff switching element having a first electrode connected to the first-output-node, a second electrode connected to the second-node, and a third electrode supplied with an OFF level potential, and
the bistable-circuit pair includes a fourth second-node turnoff switching element having a first electrode connected to the first-output-node of the previous stage bistable circuit, a second electrode connected to the third-node, and a third electrode supplied with an OFF level potential.
24. The scanning signal line drive circuit according to claim 23 , wherein
in the previous stage bistable circuit, a level of the second-node changes to the OFF level by the first charge replenishment switching element and the fourth second-node turnoff switching element being turned to the ON state during a period in which an outputted signal from this bistable circuit is active, and
in the next stage bistable circuit, the level of the second-node changes to the OFF level by the first charge replenishment switching element and the fourth second-node turnoff switching element being turned to the ON state during the period in which an outputted signal from the previous stage bistable circuit is active.
25. The scanning signal line drive circuit according to claim 1 , wherein
all of the switching elements included in each bistable circuit are respectively constituted by thin-film transistors of an identical channel.
26. A display device, comprising:
the display unit; and
the scanning signal line drive circuit according to claim 1 .
27. The scanning signal line drive circuit according to claim 1 , wherein
each of the switching elements included in each bistable circuit is a thin-film transistor using IGZO for semiconductor layer.
28. A method of driving a plurality of scanning signal lines which are arrayed in a display unit by a scanning signal line drive circuit including a shift register, outputted signals from a plurality of bistable circuits being sequentially driven active based on a plurality of clock signals that are externally inputted and cyclically repeat a first level and a second level, the method comprising:
a first switching element control step of changing a state of a first switching element included in each bistable circuit; and
a second switching element control step of changing a state of a second switching element included in each bistable circuit,
wherein
each bistable circuit includes:
a first-input-node configured to receive an outputted signal from a bistable circuit of a stage before the each bistable circuit as a set signal;
a first-output-node connected to the scanning signal line and configured to output an outputted signal from the each bistable circuit as a scanning signal for driving the scanning signal line;
a first output control switching element having a second electrode supplied with one of the plurality of clock signals as a first clock for operation control and a third electrode connected to the first-output-node;
a first-node turnon switching element configured to change a level of a first-node to an ON level based on the set signal, the first-node being connected to a first electrode of the first output control switching element;
at least one of a first first-node turnoff switching element and a first first-output-node turnoff switching element, the first first-node turnoff switching element having a second electrode connected to the first-node and being configured to change the level of the first-node to the OFF level, the first first-output-node turnoff switching element having a second electrode connected to the first-output-node, having a third electrode supplied with an OFF level potential, and being configured to change a level of the first-output-node to the OFF level;
a second-node turnoff switching element having a second electrode connected to a second-node, having a third electrode supplied with an OFF level potential, and configured to turn the second-node to the OFF level during a period in which the first-node is to be maintained at the ON level, the second-node being connected to a first electrode of at least one of the first first-node turnoff switching element and the first first-output-node turnoff switching element;
the first switching element having a first electrode supplied with one of the plurality of clock signals as a first clock for charge replenishment and a third electrode connected to the second-node;
a capacitative element having one end connected to a third-node connected to a second electrode of the first switching element; and
the second switching element having a third electrode connected to the third-node, having a first electrode supplied with one of the plurality of clock signals as a second clock for charge replenishment, and configured to charge the capacitative element based on the second clock for charge replenishment,
the first switching element control step includes:
a first switching element turnon step of turning the first switching element to an ON state by turning the first clock for charge replenishment to the first level; and
a first switching element turnoff step of turning the first switching element to an OFF state by turning the first clock for charge replenishment to the second level,
the second switching element control step includes:
a second switching element turnon step of turning the second switching element to an ON state by turning the second clock for charge replenishment to the first level; and
a second switching element turnoff step of turning the second switching element to an OFF state by turning the second clock for charge replenishment to the second level,
during a period after the first switching element turnon step is performed until the first switching element turnoff step is performed, the second switching element turnon step and the second switching element turnoff step are not performed, and
during a period after the second switching element turnon step is performed until the second switching element turnoff step is performed, the first switching element turnon step and the first switching element turnoff step are not performed.