Satellite (GPS) assisted clock apparatus, circuits, systems and processes for cellular terminals on asynchronous networks
An electronic circuit for use with time of arrival signals from a network, including a position determination unit, a first clock, a second clock, and processing circuitry coupled to said first clock, said second clock, and said position determination unit. The processing circuitry is operable to project a relatively-accurate subsequent global time based on said first and second clocks and to then return said relatively-accurate subsequent global time to said position determination unit to facilitate a subsequent position determination by said position determination unit.
1. An electronic circuit for use with time of arrival signals from a network, the electronic circuit comprising:
a position determination unit operable to generate a global time value and to convey a first global time from said position determination unit as an output;
a first clock greater than 1 MHz, said first clock operable to be powered on and off;
a second clock less than 1 MHz having cycles; and
processing circuitry coupled to said first clock and to said second clock and to said position determination unit, said processing circuitry operable to:
measure a time interval between the time of arrival signals relative to first clock counts and measure a time interval between cycles of said second clock relative to first clock counts;
generate a number n 2 of clock counts of said first clock when said first clock is powered on and generate a number of clock counts n 3 of said second clock while said first clock is powered off; and
project a relatively-accurate subsequent global time based on said first global time and using said measure and generate operations; and
then return said relatively-accurate subsequent global time to said position determination unit to facilitate a subsequent position determination by said position determination unit; and
wherein said processing circuitry is operable to project the relatively-accurate subsequent global time as a sum of products and ratios of time intervals and counter values representing numbers n of clock beats according to a relation
t CT =t 0 +[n 1 +( n 2 /RCP 0)+ n 3 ( X RTC /RCP 0)] T cellular
where
t 0 is the first global time value,
t CT is the relatively-accurate subsequent global time from time projection,
T cellular is the time interval between the time of arrival signals,
RCPO is number of first clock counts in the time interval T cellular ,
X RTC is number of first clock counts between cycles of said second clock,
n 1 is a number of received instances of the time interval T cellular ,
n 2 is the number of first clock counts distinct from periods counted with n 1 , and
n 3 is the number of second clock periods distinct from periods counted with n 1 and n 2 .
2. The electronic circuit claimed in claim 1 for use with a network that is subject to handover between base stations or handover between channels, wherein said processing circuitry is operable to project the relatively-accurate subsequent global time including a time of arrival offset due to the handover by including the time of arrival offset in the number n 2 of clock counts of the generate operation.
3. The electronic circuit claimed in claim 1 wherein the electronic circuit is subject to Doppler effect when moving, and wherein said processing circuitry is operable to project the relatively-accurate subsequent global time encompassing time of arrival changes due to the Doppler effect.
4. The electronic circuit claimed in claim 1 for use with a network that supplies timing-advance information, wherein said processing circuitry is operable to project the relatively-accurate subsequent global time utilizing the timing-advance information.
5. The electronic circuit claimed in claim 1 wherein said first clock includes a crystal subject to crystal drift and said processing circuitry is operable to project the relatively-accurate subsequent global time including a correction for the crystal drift.
6. The electronic circuit claimed in claim 1 wherein said position determination unit includes a satellite receiver and decoder coupled by a time stamp line to said processing circuitry.
7. An electronic circuit for use with time of arrival signals from a network, the electronic circuit comprising:
a position determination unit operable to generate a global time value and to convey a first global time from said position determination unit as an output;
a first clock greater than 1 MHz, said first clock operable to be powered on and off;
a second clock less than 1 MHz having cycles; and
processing circuitry coupled to said first clock and to said second clock and to said position determination unit, said processing circuitry operable to:
measure a time interval between the time of arrival signals relative to first clock counts and measure a time interval between cycles of said second clock relative to first clock counts;
generate a number n 2 of clock counts of said first clock when said first clock is powered on and generate a number of clock counts n 3 of said second clock while said first clock is powered off; and
project a relatively-accurate subsequent global time based on said first global time and using said measure and generate operations; and
then return said relatively-accurate subsequent global time to said position determination unit to facilitate a subsequent position determination by said position determination unit; and
wherein said signals have frames and intra-frame intervals that span plural periods of the first clock, and said processing circuitry is operable to project the relatively-accurate subsequent global time by also keeping a separate count n 4 of an intra-frame number IFN of the intra-frame intervals and according to a relation
t CT =t 0 +( n 1 −1)× T cellular +n 4 ×T ifn +n 2 ×T on — clock +n 3 ×T sleep — Clock
where
t 0 is the first global time value,
t CT is the relatively-accurate subsequent global time from time projection,
T cellular is the time interval between the time of arrival signals,
T on — clock is the time period of the first clock,
T sleep — Clock is the time period of the second clock,
T ifn is the time interval of each intra-frame interval,
n 1 −1 is a number of receiver synchronization instances (RSIs) spaced by T cellular ,
n 2 is the number of first clock counts distinct from periods counted with n 1 , and
n 3 is the number of second clock periods distinct from periods counted with n 1 and n 2 .
8. The electronic circuit claimed in claim 1 wherein said processing circuitry is operable to transition from count n 3 to count n 2 on a pulse boundary of said second clock.
9. The electronic circuit claimed in claim 1 wherein said processing circuitry has counters and plural modes of operation wherein the counters are selectively operated.
10. The electronic circuit claimed in claim 9 wherein a particular said mode of operation includes counters for n 2 and n 3 selected and counting depending on processing circuitry being awake or asleep respectively, and a counter for n 1 of receiver synchronization instances is in retention.
11. The electronic circuit claimed in claim 9 wherein a particular said mode of operation includes counters for n 3 and n 2 in retention and a counter for a number n 1 of receiver synchronization instances is selected and counting.
12. The electronic circuit claimed in claim 7 for use with a network that is subject to handover between base stations or handover between channels, wherein said processing circuitry is operable to project the relatively-accurate subsequent global time including a time of arrival offset due to the handover by including the time of arrival offset in the number n 2 of clock counts of the generate operation.
13. The electronic circuit claimed in claim 7 wherein the electronic circuit is subject to Doppler effect when moving, and wherein said processing circuitry is operable to project the relatively-accurate subsequent global time encompassing time of arrival changes due to the Doppler effect.
14. The electronic circuit claimed in claim 7 for use with a network that supplies timing-advance information, wherein said processing circuitry is operable to project the relatively-accurate subsequent global time utilizing the timing-advance information.
15. The electronic circuit claimed in claim 7 wherein said first clock includes a crystal subject to crystal drift and said processing circuitry is operable to project the relatively-accurate subsequent global time including a correction for the crystal drift.
16. The electronic circuit claimed in claim 7 wherein said position determination unit includes a satellite receiver and decoder coupled by a time stamp line to said processing circuitry.
17. The electronic circuit claimed in claim 7 wherein said processing circuitry is operable to transition from count n 3 to count n 2 on a pulse boundary of said second clock.
18. The electronic circuit claimed in claim 7 wherein said processing circuitry has counters and plural modes of operation wherein the counters are selectively operated.
19. The electronic circuit claimed in claim 18 wherein a particular said mode of operation includes counters for n 2 and n 3 selected and counting depending on processing circuitry being awake or asleep respectively, and a counter for n 1 of receiver synchronization instances is in retention.
20. The electronic circuit claimed in claim 18 wherein a particular said mode of operation includes counters for n 3 and n 2 in retention and a counter for a number n 1 of receiver synchronization instances is selected and counting.