Method for semiconductor sensor structures with reduced dislocation defect densities
Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.
1. A method comprising:
forming a first trench in a crystalline semiconductor substrate;
forming a second trench in a dielectric material in the first trench;
forming a crystalline material in the second trench, the crystalline material being lattice-mismatched to the crystalline semiconductor substrate; and
forming a photodetector formed at or in the crystalline material to output electrons generated by light absorption therein.
2. The method of claim 1 , wherein the photodetector is a p-n junction or p-i-n structure.
3. The method of claim 1 , comprising:
a p-i-n structure formed within the first trench; and
an intrinsic region of the p-i-n structure is positioned to receive light in the photodetector.
4. The method of claim 1 , wherein at least two photodetectors are formed in an array configuration, said array forming a photo-electronic conversion array.
5. The method of claim 1 , further comprising:
passivating at least a portion of the first trench in the crystalline substrate forming the second trench.
6. The method of claim 1 , wherein forming the crystalline material comprises defects arising from the lattice-mismatch to the crystalline substrate, the defects being trapped at sidewalls of at least one of the first trench and the second trench.
7. The method of claim 1 , wherein at least one of the first trench and the second trench has an aspect ratio of 0.5 or higher.
8. The method of claim 1 , further comprising forming a CMOS device in or on a top surface of the crystalline substrate, a top surface of the photodetector being co-planar to the CMOS device.
9. A method comprising:
providing a substrate comprising a first crystalline semiconductor material;
forming a recess in the substrate to a depth below a top surface of the first crystalline semiconductor material, the recess having an insulator sidewall;
forming a second crystalline semiconductor material in the recess that is lattice mismatched to the first crystalline semiconductor material; and
forming a light-sensing device at or in at least a portion of the second crystalline semiconductor material; and
forming an active device in or on a portion the first crystalline semiconductor material of the substrate.
10. The method of claim 9 , wherein the active device is electrically coupled to the light-sensing device.
11. The method of claim 9 , wherein the light-sensing device is a lateral p-i-n structure.
12. The method of claim 9 , wherein the light-sensing device is a lateral p-n structure.
13. The method of claim 9 , wherein the second crystalline semiconductor material comprises defects arising from the lattice mismatch to the first crystalline semiconductor material, the defects terminating in the recess.
14. A method comprising:
forming an insulator having a first opening and a second opening to a substrate, the substrate comprising a first crystalline material;
forming a second crystalline material within the first opening and the second opening, the second crystalline material coalescing between the first opening and the second opening over a lateral surface of the insulator, the second crystalline material being lattice-mismatched with the first crystalline material;
forming a light-sensing device in a portion of the second crystalline material over the lateral surface of the insulator; and
forming an active device in or on a portion the first crystalline material of the substrate, the active device being at least laterally separated from the light-sensing device.
15. The method of claim 14 , wherein the insulator is formed in a recess of the first crystalline material of the substrate.
16. The method of claim 14 , wherein a top surface of the second crystalline material is co-planar with a top surface of the first crystalline material of the substrate.
17. The method of claim 14 , wherein defects in the second crystalline material arising from the lattice-mismatch terminate in the first opening and the second opening.
18. The method of claim 14 , wherein a bottom portion of the light-sensing device is formed below a top surface of the first crystalline material of the substrate, and a top portion of the light-sensing device is formed below the top surface of the first crystalline material of the substrate.
19. The method of claim 14 further comprising electrically coupling the light-sensing device with the active device.
20. The method of claim 14 , wherein the light-sensing device comprises a lateral p-n junction or a lateral p-i-n structure.