Nonvolatile memory device and method of manufacturing the same
A nonvolatile memory device includes a substrate including a cell region, contact regions and dummy contact regions. The contact regions and the dummy contact regions alternately are disposed. A plurality of word lines stacked at the cell region of the substrate and contact groups stacked at the contact regions and the dummy contact regions of the substrate. The contact groups include a plurality of pad layers being coupled to the word lines, and each of the contact groups has stepped structure disposed at a corresponding contact region.
1. A nonvolatile memory device, comprising:
a substrate including a cell region, contact regions and dummy contact regions, where the contact regions and the dummy contact regions alternately are disposed;
a plurality of word lines stacked at the cell region of the substrate;
contact groups stacked at the contact regions and the dummy contact regions of the substrate, where the contact groups include a plurality of pad layers being coupled to the word lines, and each of the contact groups has stepped structure disposed at a corresponding contact region.
2. The nonvolatile memory device of claim 1 , further comprising:
dummy contact structures disposed at the dummy contact regions of the substrate, where each of the dummy contact structures has a side facing the stepped structure of a corresponding contact group and symmetrical with respect to the stepped structure of the corresponding contact group.
3. The nonvolatile memory device of claim 2 , where the contact groups and the dummy contact structures are spaced apart from each other at a specific interval.
4. A method of manufacturing a nonvolatile memory device, the method comprising:
forming stack groups on a substrate including contact regions and dummy contact regions alternately disposed, each of the stack groups comprising a plurality of stack layers, where each stack layer, of the plurality of stack layers, includes a first material layer and a second material layer; and
forming stepped structures, each having a plurality of steps, where each step, of the plurality of steps, is formed using one of the plurality of stack layers, and where the stepped structures are patterned, in the contact regions, from corresponding stack groups.
5. The method of claim 4 , where forming the stepped structures comprises:
forming a first stepped structure by patterning the plurality of stack layers, of each of the stack groups, using a first mask pattern so that the stack groups form steps of the first stepped structure; and
forming a second stepped structure by patterning the plurality of stack layers, of each of the plurality of stack groups, using a second mask pattern so that the stack layers form steps of the second stepped structure.
6. The method of claim 5 , where forming the second step structure further comprises:
forming dummy stack structures in the dummy contact regions.
7. The method of claim 6 , where each of the dummy stack structures has a side facing the second stepped structure of a corresponding stack group and symmetrical with respect to the second stepped structure of the corresponding stack group.
8. The method of claim 4 , where:
each of the dummy contact regions has a width that is greater than a width of each of the contact regions.
9. The method of claim 6 , where:
a width of a portion of the second mask pattern, which covers each of the contact regions is substantially the same as a width of a portion of the second mask pattern, which covers each of the dummy contact regions.
10. The method of claim 6 , where forming the first stepped structure further comprises:
forming the first mask pattern over the stack layers;
etching the plurality of stack layers using the first mask pattern to expose a lowermost stack group, from among the stack groups, corresponding to a contact region, where the lowermost stack group forms a first step in the first stepped structure; and
performing a series of etching steps, where each of the series of etching steps exposes a next highest stack group, until a penultimate stack group is exposed,
where a size of the first mask pattern is reduced with each subsequent etching step.
11. The method of claim 4 , where:
the first material layer is an interlayer insulating layer, and
the second material layer is a conductive layer.
12. The method of claim 4 , where:
the first material layer is a sacrificial layer, and
the second material layer is an interlayer insulating layer.
13. The method of claim 12 , further comprising:
removing the sacrificial layer after the corresponding stack groups are patterned to form the stepped structures; and
filling regions from which the sacrificial layer has been removed with a conductive layer.
14. The method of claim 4 , where:
the first material layer is a conductive layer, and
the second material layer is a sacrificial layer.
15. The method of claim 14 , further comprising:
removing the sacrificial layer after the corresponding stack groups are patterned to form the stepped structures; and
filling regions from which the sacrificial layer has been removed with an interlayer insulating layer.