IC state machine controlling communicating data over TDI/TDO or TMS
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
1. An integrated circuit comprising:
A. a communications interface that includes a test data in lead, a test data out lead, a test clock lead, and a test mode select lead;
B. communications circuitry coupled to the leads of the communications interface and including state machine circuitry, the state machine circuitry controlling an exchange of information through the communications interface according to one of at least a first and a second communications protocol, the state machine circuitry sequencing through a first series of states that provide for the communications interface to operate according to the first communications protocol by exchanging information over the test data in lead and the test data out lead, the state machine circuitry sequencing through at least one second state that provides for the communications interface to operate according to the second communications protocol by bi-directionally exchanging information over the test mode select lead.
2. The integrated circuit of claim 1 in which the communications circuitry includes a test access port, test mode select communications circuitry, and enable gating circuitry coupled between the test access port and the test mode select communications circuitry.
3. The integrated circuit of claim 1 in which the state machine circuitry includes a state machine having the states of Test Logic Reset State, Run Test/Idle State, Select-DR Scan State, Capture-DR State, Shift-DR State, Exit1-DR State, Pause-DR State, Exit2-DR State, Update-DR State, Select-IR Scan State, Capture-IR State, Shift-IR State, Exit1-IR State, Pause-IR State, Exit2-IR State, and Update-IR State.
4. The integrated circuit of claim 1 in which the state machine circuitry includes an instruction register and a data register coupled between the test data in lead and the test data out lead.