Methods and structure for trapping requests directed to hardware registers of an electronic circuit
Methods and structure are provided for trapping incoming requests directed to hardware registers of an electronic device. The electronic device that comprises a set of hardware registers that define a configuration of the electronic device, circuitry that implements programmable logic defining which hardware registers have been flagged for trapping incoming requests, and a shadow memory that includes values corresponding to the flagged hardware registers. The circuitry is further operable to access a value in shadow memory that corresponds to a flagged hardware register, responsive to receiving a request from an external device to access the flagged hardware register.
1. An electronic device comprising:
a set of hardware registers that define a configuration of the electronic device;
circuitry that implements programmable logic defining which hardware registers have been flagged for trapping incoming requests; and
a shadow memory that includes values corresponding to the flagged hardware registers,
the circuitry further operable to access a value in the shadow memory that corresponds to a flagged hardware register, responsive to receiving a request from an external device to access the flagged hardware register.
2. The device of claim 1 wherein
the circuitry is further operable to trap incoming read requests directed to the flagged hardware register, and to return the value in the shadow memory instead of the flagged hardware register.
3. The device of claim 1 wherein
the circuitry is further operable to trap incoming write requests directed to the flagged hardware register and to alter the value in the shadow memory.
4. The device of claim 1 wherein
the device further comprises:
a processor; and
firmware operable on the processor; and
the circuitry is further operable to determine, based on the programmable logic, whether to invoke the firmware to process the received request.
5. The device of claim 4 wherein
the circuitry is further operable to invoke the firmware by generating an interrupt at the processor.
6. The device of claim 4 wherein
the circuitry is further operable to determine a time taken by the firmware in generating the value in the shadow memory, and is further operable to return a completion to the external device responsive to determining that the time taken by the firmware exceeds a threshold.
7. The device of claim 1 wherein
the device is a Peripheral Component Interconnect express (PCIe) device, the hardware registers define a PCIe configuration space of the device, and the requests are received via a PCIe interface of the device.
8. The device of claim 1 wherein
the value in the shadow memory does not equal the value of the corresponding flagged hardware register.
9. The device of claim 1 wherein
the programmable logic includes two bits for each hardware register:
a first bit indicating whether to trap incoming read requests; and
a second bit indicating whether to trap incoming write requests.
10. The device of claim 9 wherein
the programmable logic includes two additional bits for each hardware register:
a first additional bit indicating whether to generate an interrupt for incoming read requests; and
a second additional bit indicating whether to generate an interrupt for incoming write requests.
11. A method of operating an electronic device, the method comprising:
receiving a request from an external device to access a hardware register that defines a configuration of the electronic device;
determining via circuitry at the electronic device, based on internal programmable logic, if the hardware register has been flagged for trapping incoming requests;
accessing, via the circuitry, the hardware register responsive to determining that the hardware register is not flagged; and
accessing, via the circuitry, a value in a shadow memory of the electronic circuit responsive to determining that the hardware register is flagged.
12. The method of claim 11 wherein
the request is a read request and accessing the value in the shadow memory comprises:
trapping the incoming read request directed to the flagged hardware register; and
returning the value in shadow memory instead of the value in the flagged hardware register.
13. The method of claim 11 wherein
the request is a write request and accessing the value in the shadow memory comprises:
trapping the incoming write request directed to the flagged hardware register; and
altering the value in the shadow memory.
14. The method of claim 11 further comprising
determining, based on the programmable logic, whether to invoke firmware at a processor of the electronic device to process the received request.
15. The method of claim 14 further comprising
invoking the firmware by generating an interrupt at the processor.
16. The method of claim 14 further comprising
determining a time taken by the firmware in generating the value in the shadow memory; and
returning a completion to the external device responsive to determining that the time taken by the firmware exceeds a threshold.
17. The method of claim 11 wherein
the device is a Peripheral Component Interconnect express (PCIe) device, the hardware registers define a PCIe configuration space of the device, and the requests are received via a PCIe interface of the device.
18. A non-transitory computer readable medium embodying programmed instructions which, when executed by a processor, are operable for performing a method comprising:
receiving a request from an external device to access a hardware register that defines a configuration of the electronic device;
determining via circuitry at the electronic device, based on internal programmable logic, if the hardware register has been flagged for trapping incoming requests;
accessing, via the circuitry, the hardware register responsive to determining that the hardware register is not flagged; and
accessing, via the circuitry, a value in a shadow memory of the electronic circuit responsive to determining that the hardware register is flagged.
19. The medium of claim 18 wherein
the request is a read request and accessing the value in the shadow memory comprises:
trapping the incoming read request directed to the flagged hardware register; and
returning the value in shadow memory instead of the value in the flagged hardware register.
20. The medium of claim 18 wherein
the request is a write request and accessing the value in the shadow memory comprises:
trapping the incoming write request directed to the flagged hardware register; and
altering the value in the shadow memory.