Device for the parallel processing of a data stream

1. A device for processing a data stream comprising matrices of Nl rows by Nc columns of data, said device comprising:

K computation tiles; and

interconnection means for transferring said data stream between the computation tiles, wherein at least one of the computation tiles comprises:

one or more control units to provide instructions to be executed on a subset of Vl rows by (n+Vc−1) columns of said matrix of data, said subset being called a neighborhood;

n processing units, each processing unit executing the instructions received from a control unit on the data stored in a neighborhood register when the accesses to neighborhood registers are authorized;

a storage unit to arrange the data of the stream in the form of neighborhoods of Vl rows by (n+Vc−1) columns of data, the storage unit comprising a block of shaping memories comprising Vl×Nc memory cells arranged according to a mesh of Vl rows and Nc columns and a block of neighborhood registers having a number equal to Vl×(n+Vc−1) of neighborhood registers, wherein said storage unit is configured in such a way that, at each clock, cycle, a column of Vl data of a block of shaping memories is copied to a block of neighborhood register and the accesses to neighborhood registers for processing units are disabled during the copying of a new column of data; and

an input/output unit to convey the data stream between the interconnection means and the storage unit on the one hand, and between the processing units and the interconnection means on the other hand.

2. The device as claimed in claim 1 , wherein the block of neighborhood registers further comprises a supplemental column of Vl data registers, said storage unit being configured in such a way that, at each clock cycle, a column of Vl data of a block of shaping memories is copied to said supplemental column of data registers.

3. The device as claimed in claim 2 , wherein the column of data of the block of shaping memories labeled by the value of the first counter CPTC is copied, at each clock tick of the data stream, into the column of Vl data registers and then shifted in a first column of the block of neighborhood registers.

4. The device as claimed in claim 3 , wherein each datum of the block of shaping memories situated in the column labeled by the value of the first counter CPTC and in the row labeled by RowNo is copied into the column of Vl data registers in the row labeled by (CPTL+RowNo+1) modulo Vl, where RowNo takes all the positive integer values lying between 1 and Vl.

5. The device as claimed in claim 3 , wherein the control units each comprise a memory in which is stored a program, the program possibly being split up into code segments, each code segment comprising different instructions for allowing a different processing of the data of the stream as a function of their nature.

6. The device as claimed in claim 5 , wherein the data stream originates from a video sensor delivering images of Nc columns by Nl rows of pixels, each image comprising an alternation of two types of rows, each type of row comprising two types of pixels, at least one computation tile comprising two control units, the program of each of these control units being split up into four code segments, each code segment corresponding to the various types of pixels to be taken into account.

7. The device as claimed in claim 6 , wherein the type of pixel depends on its color.

8. The device as claimed in claim 6 , wherein at least one of the computation tiles comprises:

a storage unit to store data of the stream;

a control unit to provide instructions for carrying out a processing on the stored data;

one or more processing units, each processing unit carrying out the instructions received from the control unit on a part of the stored data; and

an input/output unit to convey the data stream between the interconnection means and the storage unit on the one hand, and between the processing units and the interconnection means on the other hand, wherein

the storage unit comprises an equal number of data registers to the number of processing units.

9. The device as claimed in claim 6 , wherein the interconnection means comprises a number Nb_bus of data buses defined by the relation:

Nb _bus= Kx ( F pixel /F archi )+1

where F pixel is a frequency of the data stream and F archi is an operating frequency of the processing units (UT), the frequency F archi being equal to

p×F pixel

with p being a positive integer.

10. The device as claimed in claim 9 , wherein the input/output units each comprise Nb_bus registers of size log 2(Mux_t) bits to manage the write-access authorizations, a register of size log 2(Nb_bus) bits and a register of size log 2(Mux_t) bits for the management of the read-access authorizations, Mux_t being defined by the relation

Mux — t=F archi /F pixel .

11. The device as claimed in claim 10 , wherein the computation tiles are addressed by a temporal multiplexing whose ratio is defined by the relation:

Mux — t=F archi /F pixel .

12. The device as claimed in claim 10 , wherein the computation tiles each comprise a serial block comprising an equal number of data registers to the number of processing units of the computation tile considered, each serial block of a computation tile receiving, as input, data originating from the processing units of the computation tile considered and being connected at output to the input/output unit of said computation tile.

13. The device as claimed in claim 10 , wherein the processing units each comprise a processor comprising:

two instruction decoders;

a first set of multiplexers;

computation operators;

a second set of multiplexers;

data registers; and

a local memory, wherein

the instruction decoders receive instructions originating from a control unit,

the first set of multiplexers direct the data to be processed on one or two computation operators of the set of the available operators,

the second set of multiplexers direct the processed data toward the data registers, and

the processor executes up to two instructions per clock cycle of the processor.

14. The device as claimed in claim 10 , wherein data of the stream are concatenated with a complementary datum, computation tiles being able to dissociate the data of the stream from the complementary datum so that the processing units of said computation tiles carry out instructions on the data of the stream as a function of the complementary datum.

15. The device as claimed in claim 14 , wherein the concatenation of data of the stream with a complementary datum is carried out by an insertion operator inserted on the interconnection means.

16. The device as claimed in claim 1 , further comprising a first counter CPTC and a second counter CPTL, the first counter CPTC being incremented after each incoming datum and being reset to zero each time it reaches the value Nc, the second counter CPTL being incremented each time the first counter CPTC reaches the value Nc and being reset to zero each time it reaches the value Vl, the incoming datum being stored in a cell of the block of shaping memories whose row index corresponds to the value of the second counter CPTL and whose column index corresponds to the value of the first counter CPTC.