IP Library Granted Patent US 8,855,181
Granted Patent B2
US 8,855,181 · App. 13/760,198 · Granted Oct 7, 2014

Method and system for compensating a delay mismatch between a first measurement channel and a second measurement channel

Inventor: Jens Barrenscheen (Munich, DE)
Assignee: Infineon Technologies AG
H04L7/0033H03M1/12H02P27/08
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,855,181
App. No.
13/760,198
Granted
Oct 7, 2014
Kind
B2
Abstract

A method and a system for compensating a delay mismatch between a first measurement channel and a second measurement channel is disclosed. A method for compensating a delay mismatch between a first measurement channel and a second measurement channel includes providing a reference point for starting the first and second measurement channel, and starting the first measurement channel after expiration of a first delay period which begins at the reference point. The method further includes starting the second measurement channel after expiry of a second delay period which begins at the reference point, wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.

Claims (54)

1. A method for compensating a delay mismatch between a first measurement channel and a second measurement channel, comprising:

providing a reference point for starting the first measurement channel and the second measurement channel;

starting the first measurement channel after expiration of a first delay period which begins at the reference point; and

starting the second measurement channel after expiration of a second delay period which begins at the reference point;

wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.

2. The method of claim 1 , wherein the delay mismatch between the first measurement channel and the second measurement channel is determined in a reference measurement, wherein reference measurement input values are applied to the first measurement channel and the second measurement channel.

3. The method of claim 1 , wherein the first delay period is set and/or adjusted using a first timer structure and the second delay period is set and/or adjusted using a second timer structure.

4. The method of claim 1 , wherein a first sigma-delta analog to digital converter (ADC) is comprised in the first measurement channel and a second sigma-delta ADC is comprised in the second measurement channel.

5. The method of claim 4 , wherein the first delay period is set and/or adjusted using a first timer structure in the first measurement channel and the second delay period is set and/or adjusted using a second timer structure in the second measurement channel; and

a first decimation counter of the first sigma-delta ADC is started after the first delay period and a second decimation counter of the second sigma-delta ADC is started after the second delay period.

6. The method of claim 4 , wherein a first number of decimation samples output by a first decimation filter of the first sigma-delta ADC are discarded, wherein the first number of discarded decimation samples is adjustable to further adjust the first delay period, and wherein a second number of decimation samples output by a second decimation filter of the second sigma-delta ADC are discarded, wherein the second number of discarded decimation samples is adjustable to further adjust the second delay period, and wherein the first number of discarded decimation samples and the second number of discarded decimation samples are the same or are different.

7. The method of claim 4 , wherein the first delay period is set and/or adjusted by reloading a first decimation counter of the first sigma-delta ADC with a first adjustable value and the second delay period is set and/or adjusted by reloading a second decimation counter of the second sigma-delta ADC with a second adjustable value.

8. The method of claim 7 , wherein a first number of decimation samples output by a first decimation filter of the first sigma-delta ADC are discarded, wherein the first number of discarded decimation samples is adjustable to further adjust the first delay period, and wherein a second number of decimation samples output by a second decimation filter of the second sigma-delta ADC are discarded, wherein the second number of discarded decimation samples is adjustable to further adjust the second delay period, and wherein the first number of discarded decimation samples and the second number of discarded decimation samples are the same or are different.

9. A system for compensating a delay mismatch between a first measurement channel and a second measurement channel, the system comprising:

first means for starting the first measurement channel after expiration of a first delay period starting at a predefined reference point; and

second means for starting the second measurement channel after expiration of a second delay period starting at the predefined reference point;

wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.

10. The system of claim 9 , wherein the delay mismatch between the first measurement channel and the second measurement channel is determined in a reference measurement, wherein reference measurement input values are applied to the first measurement channel and the second measurement channel.

11. The system of claim 9 , wherein:

the first means for starting the first measurement channel after expiration of the first delay period comprises a first timer structure;

the second means for starting the second measurement channel after expiration of the second delay period comprises a second timer structure.

12. The system of claim 9 , further comprising:

a first sigma-delta analog to digital converter (ADC) comprised in the first measurement channel; and

a second sigma-delta ADC comprised in the second measurement channel, wherein:

the first means for starting the first measurement channel is configured to start a first decimation counter of the first sigma-delta ADC after expiration of the first delay period; and

the second means for starting the second measurement channel is configured to start a second decimation counter of the second sigma-delta ADC after expiration of the second delay period.

13. The system of claim 9 , further comprising:

a first sigma-delta analog to digital converter (ADC) comprised in the first measurement channel; and

a second sigma-delta ADC comprised in the second measurement channel, wherein:

the first means for starting the first measurement channel is configured to set and/or adjust the first delay period by reloading a first decimation counter of the first sigma-delta ADC with a first adjustable value, and

the second means for starting the second measurement channel is configured to set and/or adjust the second delay period by reloading a second decimation counter of the second sigma-delta ADC with a second adjustable value.

14. The system of claim 13 , wherein:

the first sigma-delta ADC is configured to discard a first number of decimation samples output by a first decimation filter of the first sigma-delta ADC, and

the second sigma-delta ADC is configured to discard a second number of decimation samples output by a second decimation filter of the second sigma-delta ADC,

wherein the first number of discarded decimation samples is adjustable to further adjust the first delay period and the second number of discarded decimation samples is adjustable to further adjust the second delay period, and wherein the first number of discarded decimation samples and the second number of discarded decimation samples are the same or are different.

15. A system for compensating a delay mismatch between a first measurement channel and a second measurement channel, the system comprising a first sigma-delta analog to digital converter (ADC) comprised in the first measurement channel and a second sigma-delta ADC comprised in the second measurement channel, wherein:

a first decimation counter of the first sigma-delta ADC is started after expiration of a first delay period starting at a predefined reference point; and

a second decimation counter of the second sigma-delta ADC is started after expiration of a second delay period starting at the predefined reference point;

wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.

16. The system of claim 15 , wherein the delay mismatch between the first measurement channel and the second measurement channel is determined in a reference measurement, wherein reference measurement input values are applied to the first measurement channel and the second measurement channel.

17. The system of claim 15 , further comprising:

a first timer structure in the first measurement channel configured to set and adjust the first delay period;

a second timer structure in the second measurement channel configured to set and adjust the second delay period.

18. The system of claim 15 , wherein the first delay period is set and/or adjusted by reloading the first decimation counter of the first sigma-delta ADC with a first adjustable value and the second delay period is set and/or adjusted by reloading the second decimation counter of the second sigma-delta ADC with a second adjustable value.

19. The system of claim 15 , wherein:

the first sigma-delta ADC is configured to discard a first number of decimation samples output by a first decimation filter of the first sigma-delta ADC, and

the second sigma-delta ADC is configured to discard a second number of decimation samples output by a second decimation filter of the second sigma-delta ADC,

wherein the first number of discarded decimation samples is adjustable to further adjust the first delay period and the second number of discarded decimation samples is adjustable to further adjust the second delay period, and wherein the first number of discarded decimation samples and the second number of discarded decimation samples are the same or are different.

20. A system for compensating a delay mismatch between a first measurement channel and a second measurement channel, wherein the system is operable to:

provide a reference point for starting the first measurement channel and the second measurement channel;

start the first measurement channel after expiration of a first delay period which begins at the reference point; and

start the second measurement channel after expiration of a second delay period which begins at the reference point;

wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.

21. The system of claim 20 , wherein the delay mismatch between the first measurement channel and the second measurement channel is determined in a reference measurement, wherein reference measurement input values are applied to the first measurement channel and the second measurement channel.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2013
From: BARRENSCHEEN, JENS
To: INFINEON TECHNOLOGIES AG
Reel/Frame 029951/0646 →
Continuity (2)
Provisional Application 61602979 · Feb 24, 2012
Related Publication 20130223497A1 · Aug 29, 2013