Hazard prevention for data conflicts between level one data cache line allocates and snoop writes
A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line.
1. A data processing system comprising:
a central processing unit executing program instructions to manipulate data;
a data cache connected to said central processing unit temporarily storing in a plurality of cache lines data for manipulation by said central processing unit;
a direct memory access unit connected to said central processing unit controlling data transfer, said direct memory access unit operating under control of said central processing unit to control data transfers;
a cache controller connected to said data cache capable controlling data transfers into and out of said data cache including
a cache read monitor including a plurality of entries, each entry storing an address of a cache read operation in progress, an entry initialized upon a cache read request and extinguished upon supply of data in response to said corresponding cache read request,
a direct memory access first-in-first-out stack including a plurality of entries, each entry storing an address of a corresponding direct memory access request to said data cache and an indication whether said direct memory access request is a read request or a write request, an entry initialized upon receipt of a direct memory access request and extinguished upon completion of said direct memory access request, and
a comparator connected to said cache read monitor and said direct memory access first-in-first-out stack for comparing an address of said direct memory access request in a final entry of said direct memory access first-in-first-out stack to said address of each entry of said cache read monitor if said direct memory access request is a write request, said comparator generating a stall signal to stall said direct memory access first-in-first-out stack preventing completion of any direct memory access request upon detection of a match.
2. The data processing system of claim 1 , wherein:
said comparator detects a match upon a data size of a cache line within said data cache thereby detecting a match if a direct memory access write request is to a same cache line as a cache read operation in progress.
3. The data processing system of claim 1 , further comprising:
a second level memory connected to said data cache including second level cache temporarily storing in a plurality of cache lines data for manipulation by said central processing unit and a second level local memory directly addressable by said central processing unit; and
a second level memory controller capable controlling data transfers into and out of said second level memory, said second level memory controller operable to
supply a direct memory access read request directed to an address within said second level memory to said data cache if said data cache stores a valid and dirty copy of a cache line including said address, and
supply a direct memory access write request directed to an address within said second level memory to said data cache if said data cache stores a valid copy of a cache line including said address.