Method and apparatus for supporting assignment of devices of virtual machines
A processing system includes at least one processing unit, at least one bus, and at least one device on the bus. A virtual machine monitor (VMM) in the processing system determines whether a base address register (BAR) of the device specifies a barred region size of less than one page. If the BAR specifies a barred region size of less than one page, the VMM reports to a virtual machine (VM) in the processing system, on behalf of the device, that the BAR specifies a barred region size of at least one page. In one embodiment, the bus comprises a peripheral component interconnect (PCI) bus, such as a PCI Express (PCIe) bus or a PCI Extended (PCI-X) bus. The device may be a video controller, a network interface controller (NIC), or any other suitable device. Other embodiments are described and claimed.
1. A method comprising:
determining, at a processor, that a device on a bus in a processing system has a base address register (BAR) which specifies a barred region size of less than one page; and
reporting, on behalf of the device by a virtual machine monitor (VMM), to a virtual machine (VM) in the processing system, that the BAR specifies a barred region size of at least one page, wherein a guest operating system is to directly read from and write to the device based on memory-mapped input/output (MMIO) and without any intervention from the VMM, wherein the VMM allows the VM to move a barred region in an address space of the VM but not in a physical space of the processing system.
2. A method according to claim 1 , wherein the bus comprises a communication channel selected from the group consisting of:
a peripheral component interconnect (PCI) bus;
a PCI Express (PCIe) bus; and
a PCI Extended (PCI-X) bus.
3. A method according to claim 1 , wherein the device comprises a hardware device from the group consisting of:
a video controller;
a network interface controller (NIC);
a universal serial bus (USB) controller;
a mass storage controller; and
a small computer system interface (SCSI) controller.
4. A method according to claim 1 , further comprising:
intercepting, at the virtual machine monitor (VMM), a query from the VM to the device, the query requesting BAR data from the device.
5. A method according to claim 1 , wherein the operation of reporting that the BAR specifies a barred region size of at least one page comprises:
reporting that the BAR specifies the barred region size to be at least 4096 bytes (4K).
6. A method according to claim 1 , further comprising:
configuring device BARs to place all barred regions for all devices on the bus on different pages of host physical memory.
7. The method of claim 1 , further comprising the VMM mapping a barred region of the device into an address space of the VM.
8. The method of claim 1 , further comprising the VM causing placement of a plurality of barred regions of a plurality of devices on the bus, including the device and another device, on the same memory page.
9. The method of claim 8 , wherein the plurality of the devices are assigned to the VM.
10. A method comprising:
determining whether a device on a bus in a processing system has a base address register (BAR) which specifies a barred region that will not be page aligned; and
updating the BAR, at a virtual machine monitor (VMM), to specify the barred region to be page aligned if the BAR specifies a barred region that will not be page aligned, wherein a guest operating system is to directly read from and write to the device based on memory-mapped input/output (MMIO) and without any intervention from the VMM, wherein the VMM allows a virtual machine (VM) to move a barred region in an address space of the VM but not in a physical space of the processing system.
11. A method according to claim 10 , further comprising:
configuring device BARs to place all barred regions for all devices on the bus on different pages of host physical memory.
12. An apparatus comprising:
a non-transitory machine-accessible medium; and
instructions in the machine-accessible, wherein the instructions, when executed by a processing system, cause the processing system to perform operations comprising:
determining that a device on a bus in the processing system has a base address register (BAR) which specifies a barred region size of less than one page; and
reporting, on behalf of the device by a virtual machine monitor (VMM), to a virtual machine (VM) in the processing system, that the BAR specifies a barred region size of at least one page, wherein a guest operating system is to directly read from and write to the device based on memory-mapped input/output (MMIO) and without any intervention from the VMM, wherein the VMM is to allow the VM to move a barred region in an address space of the VM but not in a physical space of the processing system.
13. An apparatus according to claim 12 , wherein the bus comprises a communication channel selected from the group consisting of:
a peripheral component interconnect (PCI) bus;
a PCI Express (PCIe) bus; and
a PCI Extended (PCI-X) bus.
14. An apparatus according to claim 12 , wherein the device comprises a hardware device from the group consisting of:
a video controller;
a network interface controller (NIC);
a universal serial bus (USB) controller;
a mass storage controller; and
a small computer system interface (SCSI) controller.
15. An apparatus according to claim 12 , wherein the instructions further cause the processing system the perform operations comprising:
if the BAR of the device specifies a barred region that will not be page aligned, updating the BAR to specify the barred region to be page aligned.
16. An apparatus according to claim 12 , wherein the instructions, when executed, implement the virtual machine monitor (VMM) to intercept a query from the VM to the device, the query requesting BAR data from the device.
17. An apparatus according to claim 12 , wherein the operation of reporting that the BAR specifies a barred region size of at least one page comprises:
reporting that the BAR specifies the barred region size to be at least 4096 bytes (4K).
18. An apparatus according to claim 12 , wherein the instructions further cause the processing system the perform operations comprising:
configuring device BARs to place all barred regions for all devices on the bus on different pages of host physical memory.
19. A system comprising:
a processing unit;
a bus responsive to the processing unit;
a device responsive to the processing unit via the bus;
a base address register (BAR) in the device;
a virtual machine (VM); and
a virtual machine monitor (VMM) to report, on behalf of the device, to the VM, that the BAR specifies a barred region size of at least one page, wherein a guest operating system is to directly read from and write to the device based on memory-mapped input/output (MMIO) and without any intervention from the VMM, wherein the VMM allows the VM to move a barred region in an address space of the VM but not in a physical space of the processing system.
20. A system according to claim 19 , wherein the bus comprises a communication channel selected from the group consisting of:
a peripheral component interconnect (PCI) bus;
a PCI Express (PCIe) bus; and
a PCI Extended (PCI-X) bus.
21. A system according to claim 19 , wherein the device comprises a hardware device from the group consisting of:
a video controller;
a network interface controller (NIC);
a universal serial bus (USB) controller;
a mass storage controller; and
a small computer system interface (SCSI) controller.
22. A system according to claim 19 , further comprising:
control logic in the VMM to determine whether the BAR of the device specifies a barred region that will not be page aligned, and to update the BAR to specify the barred region to be page aligned if the BAR specifies a barred region that will not be page aligned.
23. A system according to claim 19 , further comprising:
control logic in the VMM to intercept a query from the VM to the device, the query requesting BAR data from the device.
24. A system according to claim 19 , further comprising:
control logic in the VMM to configure device BARs to place all barred regions for all devices on the bus on different pages of host physical memory.