Semiconductor storage device
A semiconductor storage device includes a semiconductor substrate and an active area on the semiconductor substrate. A plurality of cell transistors are formed on the active area. A first bit line and a second bit line are paired with each other. A plurality of word lines intersect the first and second bit lines. A plurality of storage elements respectively has a first end electrically connected to a source or a drain of one of the cell transistors and a second end connected to the first or second bit line. Both of the first and second bit lines are connected to the same active area via the storage elements.
1. A semiconductor storage device comprising:
a semiconductor substrate;
an active area on the semiconductor substrate;
a plurality of cell transistors on the active area;
a pair of a first bit line and a second bit line which are adjacent to each other;
a plurality of word lines intersecting the first and second bit lines; and
a plurality of storage elements respectively having a first end electrically connected to a source or a drain of one of the cell transistors and a second end connected to the first or second bit line, wherein
both of the first and second bit lines are connected to the same active area via the storage elements, wherein
the cell transistors respectively have one end directly connected to the first bit line via one of the storage elements and the other end directly connected to the second bit line via one of the storage elements.
2. The device of claim 1 , wherein
during a data reading operation or a data writing operation,
when one first storage element connected to the first bit line is selected from the storage elements, a current flows to the first storage element via a plurality of second storage elements, among the storage elements, connected to the second bit line, and
when one of the second storage elements connected to the second bit line is selected from the storage elements, a current flows to the one second storage element via a plurality of the first storage elements, among the storage elements, connected to the first bit line.
3. The device of claim 1 , wherein a connection between the first bit line and the active area and a connection between the second bit line and the active area are all established via the storage elements.
4. The device of claim 2 , wherein a connection between the first bit line and the active area and a connection between the second bit line and the active area are all established via the storage elements.
5. The device of claim 1 , wherein
two word lines on both sides of one of the first storage elements connected to the first bit line is adjacent to two of the second storage elements connected to the second bit line, and
two of the cell transistors are provided between the one first storage element and the two second storage elements, respectively.
6. The device of claim 2 , wherein
two word lines on both sides of one of the first storage elements connected to the first bit line is adjacent to two of the second storage elements connected to the second bit line, and
two of the cell transistors are provided between the one first storage element and the two second storage elements, respectively.
7. The device of claim 3 , wherein
two word lines on both sides of one of the first storage elements connected to the first bit line is adjacent to two of the second storage elements connected to the second bit line, and
two of the cell transistors are provided between the one first storage element and the two second storage elements, respectively.
8. The device of claim 1 , wherein the storage elements commonly connected to the same active area are provided on both sides of each of the word lines.
9. The device of claim 2 , wherein the storage elements commonly connected to the same active area are provided on both sides of each of the word lines.
10. The device of claim 1 , wherein
one end of a first storage element among the storage elements is connected to the first bit line,
the other end of the first storage element is connected to one of a source and a drain of a first cell transistor among the cell transistors,
one end of a second storage element among the storage elements is connected to the source and the drain of the first cell transistor, and
the other end of the second storage element is connected to the second bit line.
11. The device of claim 2 , wherein
one end of a first storage element among the storage elements is connected to the first bit line,
the other end of the first storage element is connected to one of a source and a drain of a first cell transistor among the cell transistors,
one end of a second storage element among the storage elements is connected to the source and the drain of the first cell transistor, and
the other end of the second storage element is connected to the second bit line.
12. The device of claim 3 , wherein
one end of a first storage element among the storage elements is connected to the first bit line,
the other end of the first storage element is connected to one of a source and a drain of a first cell transistor among the cell transistors,
one end of a second storage element among the storage elements is connected to the source and the drain of the first cell transistor, and
the other end of the second storage element is connected to the second bit line.
13. The device of claim 1 , wherein the first and second bit lines are formed out of a common wiring layer.
14. The device of claim 1 , wherein the first and second bit lines are formed out of different wiring layers, respectively.
15. The device of claim 1 , wherein the storage elements are magnetic tunnel junction elements.
16. The device of claim 1 , wherein a connection between the first bit line and the source or the drain of one of the cell transistors and a connection between the second bit line and the source or the drain of the one cell transistor are established via the storage elements.
17. The device of claim 16 , wherein a connection between the first bit line and the source or the drain of each of the cell transistors and a connection between the second bit line and the source or the drain of each of the cell transistors are all established via the storage elements.