Interface circuit
According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor.
1. An interface circuit comprising:
an output buffer electrically coupled to a pad electrode, the output buffer including a first transistor and a second transistor, the output buffer being configured to output waveform on the basis of the ON/OFF operation of the first transistor and the second transistor; and
a driver circuit which is capable of independently changing a turn-ON speed or a turn-OFF speed of at least one of the first transistor and the second transistor.
2. The interface circuit according to claim 1 ,
wherein the driver circuit includes a slew rate control unit which is capable of changing the turn-ON speed of at least one of the first transistor and the second transistor, and a reset rate control unit which is capable of changing the turn-OFF speed of at least one of the first transistor and the second transistor.
3. The interface circuit according to claim 2 ,
wherein the first transistor is a first P-channel field-effect transistor and the second transistor is a first N-channel field-effect transistor which is connected to the first P-channel field-effect transistor in series, and
the driver circuit is provided with a P-slew rate control unit which is capable of changing a turn-ON speed of the first P-channel field-effect transistor, a P-reset rate control unit which is capable of changing a turn-OFF speed of the first P-channel field-effect transistor, a N-slew rate control unit which is capable of changing a turn-ON speed of the first N-channel field-effect transistor, and a N-reset rate control unit which is capable of changing, a turn-OFF speed of the first N-channel field-effect transistor.
4. The interface circuit according to claim 3 , further comprising:
a time lag generation circuit which adds a period of time in order to turn off both of the first P-channel field-effect transistor and the first N-channel field-effect transistor at the same time.
5. The interface circuit according to claim 4 , further comprising:
a level shifter which is connected to a front stage of the time lag generation circuit.
6. The interface circuit according to claim 3 ,
wherein the P-slew rate control unit is provided with a second N-channel field-effect transistor which pulls down a gate potential of the first P-channel field-effect transistor on the basis of an input voltage, and a third N-channel field-effect transistor which is connected to the second N-channel field-effect transistor in series and in which a first intermediate voltage independent from the input voltage is applied to a gate terminal,
the P-reset rate control unit is provided with a second P-channel field-effect transistor which pulls up a gate potential of the first P-channel field-effect transistor on the basis of the input voltage, and a third P-channel field-effect transistor which is connected to the second P-channel field-effect transistor in series and in which a second intermediate voltage independent from the input voltage is applied to a gate terminal, the N-slew rate control unit is provided with a fourth P-channel field-effect transistor which pulls up a gate potential of the first N-channel field-effect transistor on the basis of the input voltage, and a fifth P-channel field-effect transistor which is connected to the fourth P-channel field-effect transistor in series and in which a third intermediate voltage independent from the input voltage is applied to a gate terminal, and
the N-reset rate control unit is provided with a fourth N-channel field-effect transistor which pulls down a gate potential of the first N-channel field-effect transistor on the basis of the input voltage, and a fifth N-channel field-effect transistor which is connected to the fourth N-channel field-effect transistor in series and in which a fourth intermediate voltage independent from the input voltage is applied to a gate terminal.
7. The interface circuit according to claim 6 , further comprising:
a pad electrode which is connected to an output terminal of the output buffer.
8. The interface circuit according to claim 7 ,
wherein readout data read out from a NAND flash memory is transferred to a controller.
9. The interface circuit according to claim 8 ,
wherein a plurality of semiconductor chips which have the NAND flash memory formed therein are stacked, and the pad electrode is connected between the semiconductor chips through a bonding wire.
10. The interface circuit according to claim 9 ,
wherein the semiconductor chip is provided with a resister which stores values of the first to fourth intermediate voltages, and a generator which generates the first to fourth intermediate voltages on the basis of a value of the resister.
11. The interface circuit according to claim 3 ,
wherein the P-slew rate control unit is provided with a second N-channel field-effect transistor which pulls down a gate potential of the first P-channel field-effect transistor on the basis of an input voltage, and a third N-channel field-effect transistor which is connected to the second N-channel field-effect transistor in series and in which a first intermediate voltage independent from the input voltage is applied to a gate terminal,
the P-reset rate control unit is provided with a plurality of second P-channel field-effect transistors which are connected to each other in parallel so as to pull up a gate potential of the first P-channel field-effect transistor on the basis of the input voltage, and a first selection circuit which selects the number of the second P-channel field-effect transistors to be turned on at the time of pulling-up,
the N-slew rate control unit is provided with a third P-channel field-effect transistor which pulls up a gate potential of the first N-channel field-effect transistor on the basis of the input voltage, and a fourth P-channel field-effect transistor which is connected to the third P-channel field-effect transistor in series and in which a second intermediate voltage independent from the input voltage is applied to a gate terminal, and
the N-reset rate control unit is provided with a plurality of fourth N-channel field-effect transistors which are connected to each other in parallel so as to pull down a gate potential of the first P-channel field-effect transistor on the basis of the input voltage, and a second selection circuit which selects the number of the fourth N-channel field-effect transistors to be turned on at the time of pulling-down.
12. The interface circuit according to claim 11 , further comprising:
a pad electrode which is connected to an output terminal of the output buffer.
13. The interface circuit according to claim 12 ,
wherein readout data read out from a NAND flash memory is transferred to a controller.
14. The interface circuit according to claim 13 ,
wherein a plurality of semiconductor chips which have the NAND flash memory formed therein are stacked, and the pad electrode is connected between the semiconductor chips through a bonding wire.
15. The interface circuit according to claim 14 ,
wherein the semiconductor chip is provided with a resister which stores values of the first and second intermediate voltages and values of selection signals of the first and second selection circuits, and a generator which generates the first and second intermediate voltages and the selection signals on the basis of a value of the resister.
16. The interface circuit according to claim 3 ,
wherein the P-slew rate control unit is provided with a plurality of second P-channel field-effect transistors which are connected to each other in parallel so as to pull down a gate potential of the first P-channel field-effect transistor on the basis of an input voltage, and a first selection circuit which selects the number of the second P-channel field-effect transistors to be turned on at the time of pulling-down,
the P-reset rate control unit is provided with a plurality of third P-channel field-effect transistors which are connected to each other in parallel so as to pull up a gate potential of the first P-channel field-effect transistor on the basis of the input voltage, and a second selection circuit which selects the number of the third P-channel field-effect transistors to be turned on at the time of pulling-up,
the N-slew rate control unit is provided with a plurality of second N-channel field-effect transistors which are connected to each other in parallel so as to pull up a gate potential of the first N-channel field-effect transistor on the basis of the input voltage, and a third selection circuit which selects the number of the second N-channel field-effect transistors to be turned on at the time of pulling-up, and
the N-reset rate control unit is provided with a plurality of third N-channel field-effect transistors which are connected to each other in parallel so as to pull down a gate potential of the first N-channel field-effect transistor on the basis of the input voltage, and a fourth selection circuit which selects the number of the third N-channel field-effect transistors to be turned on at the time of pulling-down.
17. The interface circuit according to claim 16 , further comprising:
a pad electrode which is connected to an output terminal of the output buffer.
18. The interface circuit according to claim 17 ,
wherein readout data read out from a NAND flash memory is transferred to a controller.
19. The interface circuit according to claim 18 ,
wherein a plurality of semiconductor chips which have the NAND flash memory formed therein are stacked, and the pad electrode is connected between the semiconductor chips through a bonding wire.
20. The interface circuit according to claim 19 ,
wherein the semiconductor chip is provided with a resister which stores values of selection signals of the first to fourth selection circuits, and a generator which generates the selection signals of the first to fourth selection circuits on the basis of a value of the resister.
21. The interface circuit according to claim 11 ,
wherein the numbers of the second P-channel field-effect transistors and the fourth N-channel field-effect transistors to be turned on are changed on the basis of a power-supply voltage or an operation speed.
22. The interface circuit according to claim 16 ,
wherein the numbers of the third P-channel field-effect transistors and the third N-channel field-effect transistors to be turned on are changed on the basis of a power-supply voltage or an operation speed.