Stream clock recovery in high definition multimedia digital system
The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.
1. A stream clock recovery device, comprising:
a sink device coupled to receive data from a link channel, the data including frequency clock data;
the sink device comprising:
a data extractor to extract the frequency clock data to obtain extracted frequency clock data;
a data calibrator to adjust the extracted frequency clock data to obtain adjusted frequency clock data;
a data translator having an integer and fraction value generator, generating an integer part and a fractional part of the adjusted frequency clock data;
a phase locked loop (PLL) for synthesizing a recovered stream clock from the integer part and the fractional part of the adjusted frequency clock data, wherein the PLL is a pulse-swallow divider, and wherein the PLL with pulse-swallow divider further comprises:
a first frequency divider for dividing an input clock ratio into a reference clock;
a second frequency divider for dividing a clock output into an output clock, wherein the second frequency divider is configured to divide by multiple factors;
a phase/frequency detector coupled to receive the reference clock and a feedback clock and to provide up and down signals;
a charge pump coupled to receive the up and down signals;
a low-pass filter coupled to an output signal of the charge pump;
a voltage controlled oscillator coupled to receive the output signal of the charge pump for frequency synthesis to generate the clock output; and
a third frequency divider and a prescaler coupled to the voltage controlled oscillator for fractional divisional control, wherein the third frequency divider is programmable and the third frequency divider generates the feedback clock; and
a sigma-delta-modulator (SDM) for generating an integer divisor for the PLL by modulating the fractional part of the clock data.
2. The stream clock recovery device of claim 1 , wherein the data calibrator includes a cycle time counter, wherein the data calibrator measures the recovered stream clock with the counter to obtain recovered clock data and compares the measured recovered clock data with the extracted clock data.
3. The stream clock recovery device of claim 1 , further comprising a calibration selection switch to choose among different calibration techniques in the data calibrator.
4. The stream clock recovery device of claim 1 , wherein the data translator provides a first divisor for the second frequency divider in the PLL, and the SDM provides a second divisor for the third frequency divider in the PLL.
5. The stream clock recovery device of claim 1 , wherein the SDM is programmable, and wherein the SDM comprises an integrator.
6. The stream clock recovery device of claim 5 , wherein the integrator comprises three series coupled integrators that are independently controllable to program the SDM.
7. The stream clock recovery device of claim 1 , further comprising a data buffer, and a data buffer filling level of the data buffer being monitored by the data calibrator periodically.
8. A method of recovering a stream clock, comprising:
extracting frequency clock data from a link channel;
adjusting the frequency clock data to obtain adjusted frequency clock data;
generating an integer part and a fractional part of the adjusted frequency clock data;
modulating the fractional part with a sigma-delta-modulator (SDM) to obtain a modulated fractional part of the adjusted frequency clock data; and
synthesizing, by a phase locked loop (PLL), a recovered stream clock from the integer part and the modulated fractional part of the adjusted frequency clock data, wherein the PLL is a pulse-swallow divider, and wherein the PLL with pulse-swallow divider further comprises:
a first frequency divider for dividing an input clock ratio into a reference clock;
a second frequency divider for dividing a clock output into an output clock, wherein the second frequency divider is configured to divide by multiple factors;
a phase/frequency detector coupled to receive the reference clock and a feedback clock and to provide up and down signals;
a charge pump coupled to receive the up and down signals;
a low-pass filter coupled to an output signal of the charge pump;
a voltage controlled oscillator coupled to receive the output signal of the charge pump for frequency synthesis to generate the clock output; and
a third frequency divider and a prescaler coupled to the voltage controlled oscillator for fractional divisional control, wherein the third frequency divider is programmable and the third frequency divider generates the feedback clock.
9. The method of claim 8 , wherein adjusting the frequency clock data includes generating recovered clock data from the recovered stream clock and comparing the recovered clock data with the frequency clock data to adjust the frequency clock data.
10. The method of claim 8 , wherein adjusting the frequency clock data includes monitoring a data buffer filling level of a data buffer.