Techniques for managing power and performance of multi-socket processors
Examples are disclosed for managing power and performance of multi-socket processors. In some examples, a utilization rate of a first processor circuitry in a first processor socket may be determined. An active memory ratio of a cache for the first processor circuitry may be compared to a threshold ratio or a data traffic rate between the first processor circuitry and a second processor circuitry in a second processor socket may be compared to a threshold rate. According to some examples, a first power state of the first processor circuitry may be changed based on the determined utilization rate. The first power state may also be changed based on the comparison of the active memory ratio to the threshold ratio or the comparison of the data traffic rate to the threshold rate.
1. A method comprising:
monitoring activity of a first processor circuitry in a first processor socket to determine a utilization rate of the first processor circuitry, the first processor circuitry coupled to a second processor in a second processor socket via one or more communication links capable of providing access to a cache for the first processor circuitry that is operated at a same clock frequency as the first processor circuitry; and
changing a first power state of the first processor circuitry based on the utilization rate.
2. The method of claim 1 , comprising:
providing access to the cache for the first processor circuitry in order to facilitate execution of an application by the second processor circuitry, the application utilizing both the cache for the first processor circuitry and a cache for the second processor circuitry while being executed by the second processor circuitry.
3. The method of claim 1 , the cache of the first processor circuitry comprising on-die volatile memory.
4. The method of claim 1 , the cache comprising a last level cache (LLC) for the first processor circuitry.
5. The method of claim 1 , the one or more communication links comprising one or more point-to-point processor interconnects.
6. The method of claim 1 , comprising:
comparing an active memory ratio of the cache for the first processor circuitry to a threshold ratio or comparing a data traffic rate between the first and second processor circuitry via the one or more communication links to a threshold rate; and
changing the first power state based on the comparison of the active memory ratio to the threshold ratio or based on the comparison of the data traffic rate to the threshold rate.
7. The method of claim 6 , the active memory ratio of the cache for the first processor circuitry comprise an amount of available active memory compared to a total memory capacity of the cache for the first processor circuitry.
8. The method of claim 6 , the data traffic rate between the first and second processor circuitry via the one or more communication links comprises an inter-socket data traffic rate associated with a number of data packets for read or write access to the cache for the first processor circuitry by the second processor circuitry over a given time period.
9. The method of claim 6 , comprising changing the first power state to a second power state that is higher than the first power state.
10. The method of claim 9 , comprising the monitored utilization rate indicating that the first processor circuitry is underutilized and the comparison of the active memory ratio to the threshold ratio indicates that the active memory ratio is higher than the threshold ratio.
11. The method of claim 9 , comprising the monitored utilization rate indicating that the first processor circuitry is underutilized and the comparison of the data traffic to the threshold rate indicates that the data traffic rate is higher than the threshold rate.
12. The method of claim 6 , comprising changing the first power state to a second power state that is lower than the first power state.
13. The method of claim 12 , comprising the monitored utilization rate indicating that the first processor circuitry is underutilized and the comparison of the active memory ratio to the threshold ratio indicates that the active memory ratio is lower than the threshold ratio.
14. The method of claim 12 , comprising the monitored utilization rate indicating that the first processor circuitry is underutilized and the comparison of the data traffic rate to the threshold rate indicating that the data traffic rate is lower than the threshold rate.
15. An apparatus comprising:
a monitor module operative to monitor a utilization rate of a first processor circuitry in a first processor socket, the first processor circuitry coupled to a second processor in a second processor socket via one or more communication links capable of providing access to a cache for the first processor circuitry that is operated within a same clock frequency or power management domain as the first processor circuitry; and
a power state module operative to change a first power state of the first processor circuitry based on the utilization rate.
16. The apparatus of claim 15 , the cache of the first processor circuitry comprising on-die volatile memory.
17. The apparatus of claim 15 , the one or more communication links comprising one or more point-to-point processor interconnects.
18. The apparatus of claim 15 , the cache comprising a last level cache (LLC) for the first processor circuitry.
19. The apparatus of claim 15 , comprising:
a comparison module operative to compare an active memory ratio of the cache for the first processor circuitry to a threshold ratio or comparing a data traffic rate between the first and second processor circuitry via the one or more communication links to a threshold rate; and
the power state module also operative to change the first power state based on the comparison of the active memory ratio to the threshold ratio or based on the comparison of the data traffic rate to the threshold rate.
20. The apparatus of claim 19 , the monitor module operative to determine that the utilization rate indicates the first processor circuitry is underutilized, the comparison module operative to determine that the comparison of the active memory ratio to the threshold ratio indicates that the active memory ratio is higher than the threshold ratio, and the power state module operative to change the first power state to a higher power state based on the monitoring module's determination and the comparison module's determination.
21. The apparatus of claim 19 , the monitor module operative to determine that the utilization rate indicates the first processor circuitry is underutilized, the comparison module operative to determine that the comparison of the data traffic rate to the threshold rate indicates that the data traffic rate is higher than the threshold rate, and the power state module operative to change the first power state to a higher power state based on the monitoring module's determination and the comparison module's determination.
22. The apparatus of claim 19 , the monitor module operative to determine that the utilization rate indicates the first processor circuitry is underutilized, the comparison module operative to determine that the comparison of the active memory ratio to the threshold ratio indicates that the active memory ratio is lower than the threshold ratio, and the power state module operative to change the first power state to a lower power state based on the monitoring module's determination and the comparison module's determination.
23. The apparatus of claim 19 , the monitor module operative to determine that the utilization rate indicates the first processor circuitry is underutilized, the comparison module operative to determine that the comparison of the data traffic rate to the threshold rate indicates that the data traffic rate is lower than the threshold rate, and the power state module operative to change the first power state to a lower power state based on the monitoring module's determination and the comparison module's determination.
24. At least one machine readable medium comprising a plurality of instructions that in response to being executed on a system cause the system to:
monitor activity of a first processor circuitry in a first processor socket to determine a utilization rate of the first processor circuitry, the first processor circuitry coupled to a second processor in a second processor socket via one or more communication links capable of providing access to a cache for the first processor circuitry that is operated at a same clock frequency as the first processor circuitry; and
cause a first power state of the first processor circuitry to be changed to a higher power state based on the utilization rate.
25. The at least one machine readable medium of claim 24 , the plurality of instructions to also cause the system to:
compare an active memory ratio of the cache for the first processor circuitry to a threshold ratio or comparing a data traffic rate between the first and second processor circuitry via the one or more communication links to a threshold rate; and
cause the first power state of the first processor circuitry to be changed to the higher power state based on the comparison of the active memory ratio to the threshold ratio or based on the comparison of the data traffic rate to the threshold rate.
26. The at least one machine readable medium of claim 25 , comprising the monitored utilization rate indicating that the first processor circuitry is underutilized and the comparison of the active memory ratio to the threshold ratio indicates that the active memory ratio is higher that the threshold ratio.
27. The at least one machine readable medium of claim 25 , comprising the monitored utilization rate indicating that the first processor circuitry is underutilized and the comparison of the data traffic to the threshold rate indicates that the data traffic rate is higher than the threshold rate.
28. The at least one machine readable medium of claim 24 , the cache of the first processor circuitry comprising on-die volatile memory.
29. The at least one machine readable medium of claim 24 , the one or more communication links comprising one or more point-to-point processor interconnects.
30. The at least one machine readable medium of claim 24 , the cache comprising a last level cache (LLC) for the first processor circuitry.