IP Library Granted Patent US 8,865,592
Granted Patent B2
US 8,865,592 · App. 12/364,804 · Granted Oct 21, 2014

Silicided semiconductor structure and method of forming the same

Inventors: Jiang Yan (Newburgh, NY); Henning Haffner (Pawling, NY); Frank Huebinger (Dresden, DE); SunOo Kim (Hopewell Junction, NY); Richard Lindsay (Beacon, NY); Klaus Schruefer (Baldham, DE)
Assignee: Infineon Technologies AG
H01L23/5256H01L21/28088H01L29/4966
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Quick Facts
Patent No.
US 8,865,592
App. No.
12/364,804
Granted
Oct 21, 2014
Kind
B2
Abstract

A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

Claims (11)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a polysilicon layer;

doping the polysilicon layer with carbon or nitrogen;

patterning the polysilicon layer to form a fuse element;

forming a metal layer prior to forming the polysilicon layer, the metal layer being removed from a region of the fuse element;

patterning the polysilicon layer to form a transistor gate, the transistor gate being spaced from the fuse element;

depositing a metal over the polysilicon layer; and

annealing the metal and the polysilicon layer to form a silicide region in an upper portion of the polysilicon layer.

2. The method of claim 1 , wherein depositing the metal over the polysilicon layer comprises depositing the metal over the fuse element and over the transistor gate, and wherein annealing forms a silicide region of a first thickness of the fuse element and a silicide region of a second thickness over the transistor gate, the first thickness being smaller than the second thickness.

3. The method of claim 2 , wherein the second thickness is substantially the same as a thickness of the transistor gate thereby forming a fully silicided gate.

4. The method of claim 1 , wherein the doping comprises ion implantation at an energy level of about 5 keV to 20 keV and an implantation dose of about 10 10 dopants/cm 2 to 10 13 dopants/cm 2 .

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2009
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
To: INFINEON TECHNOLOGIES AG
Reel/Frame 022386/0023 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2009
From: YAN, JIANG; HAFFNER, HENNING; HUEBINGER, FRANK; KIM, SUNOO; LINDSAY, RICHARD
To: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Reel/Frame 022265/0531 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2009
From: SCHRUEFER, KLAUS
To: INFINEON TECHNOLOGIES AG
Reel/Frame 022265/0557 →
Continuity (1)
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