Stack package

1. A stack package comprising:

a plurality of stacked chips; and

a chip selection controller configured to provide a reference signal and a chip selection control signal to the plurality of chips,

wherein each of the chips comprise:

a reference signal controller configured to transmit the reference signal through a first line interconnecting the plurality of chips;

a chip selection delay unit configured to control a delay timing point of the chip selection control signal in different ways so as to transmit the control result to each node of a second line interconnecting the plurality of chips;

a delay-time-difference sensing unit configured to calculate a delay time difference between a signal applied to each node of the first line and a signal applied to each node of the second line so as to generate chip selection information corresponding to the calculated delay time difference; and

a memory unit configured to store the chip selection information.

2. The stack package according to claim 1 , wherein the chip selection controller respectively supplies the reference signal and the chip selection control signal having the same delay timing point to a first node of the first line and a first node of the second line during a power-up operation.

3. The stack package according to claim 1 , wherein the delay time difference gradually increases on the second line.

4. The stack package according to claim 1 , wherein the chip selection control signal passing through the chip selection delay unit on the second line has a constant delay time difference at each node, and is sequentially enabled.

5. The stack package according to claim 1 , wherein the chip selection controller selects the corresponding chip by adjusting an enable timing point of the chip selection control signal during a normal operation.

6. The stack package according to claim 1 , wherein the chip selection controller synchronizes an enable timing point of the reference signal applied to a first node of the first line with an enable timing point of a signal applied to a specific node of the second line, such that it selects the corresponding chip.

7. The stack package according to claim 1 , wherein the reference signal controller is a Through Silicon Via (TSV) contained in the plurality of chips.

8. The stack package according to claim 1 , wherein the chip selection controller includes:

a delay unit coupled to the second line; and

a delay controller configured to delay the chip selection control signal applied to the second line, and output the delayed result to each node.

9. The stack package according to claim 8 , wherein the delay controller is coupled in parallel to the delay unit.

10. The stack package according to claim 8 , wherein the delay unit is a Through Silicon Via (TSV) contained in each of the chips.

11. The stack package according to claim 8 , wherein the delay controller includes a capacitor.

12. A stack package comprising:

a plurality of stacked chips; and

a chip selection controller configured to provide a first reference signal, a second reference signal, and a chip selection control signal to the plurality of chips,

wherein each of the chips comprise:

a first reference signal controller configured to transmit the first reference signal through a third line interconnecting the plurality of chips;

a second reference signal controller configured to transmit the second reference signal through a fourth line interconnecting the plurality of chips;

a chip selection delay unit configured to control a delay timing point of the chip selection control signal in different ways so as to transmit the control result to each node of a fifth line interconnecting the plurality of chips;

a delay-time-difference controller configured to calculate a delay time difference between a signal applied to each node of the third line and a signal applied to each node of the fourth line so as to generate chip selection information corresponding to the calculated delay time difference, and decode chip selection information; and

a memory unit configured to store the chip selection information and decoded information of the delay-time-difference controller.

13. The stack package according to claim 12 , wherein the chip selection controller supplies the first reference signal and the chip selection control signal having the same delay timing point to a first node of the third line and a first node of the fifth line during a power-up operation.

14. The stack package according to claim 12 , wherein the delay time difference gradually increases on the fifth line.

15. The stack package according to claim 12 , wherein the chip selection control signal passing through the chip selection delay unit on the fifth line has a constant delay time difference at each node, and is sequentially enabled.

16. The stack package according to claim 12 , wherein the chip selection controller selects the corresponding chip by combining the first reference signal with the second reference signal during a normal operation.

17. The stack package according to claim 12 , wherein the delay-time-difference controller selects the corresponding chip when a combination signal of the first reference signal and the second reference signal is identical to a decoded signal stored in the memory unit.

18. The stack package according to claim 12 , wherein the first reference signal controller is a resistor coupled to the third line, and the second reference signal controller is a resistor coupled to the fourth line.

19. The stack package according to claim 12 , wherein the chip selection controller includes:

a delay unit coupled to the fifth line; and

a delay controller configured to delay the chip selection control signal applied to the fifth line, and output the delayed result to each node.

20. The stack package according to claim 19 , wherein the delay controller is coupled in parallel to the delay unit.