Folded-cascode amplifier
An amplifier with gain boosting is disclosed according to an aspect of the subject technology. The gain boosting may be used to improve the noise figure of the amplifier, and may be achieved by feeding an input signal to the gates of multiple transistors in the amplifier, where each transistor provides a current gain contributing to the total current gain of the amplifier. The amplifier may also include an output driver stage for increasing the driving capability of the amplifier. The amplifier may also include a feedback resistor and an input resistor to obtain a gain with high linearity.
1. An amplifier, comprising:
a first current-gain transistor having a gate coupled to an input of the amplifier;
a second current-gain transistor having a gate coupled to the input of the amplifier via a first gain path;
a first cascode transistor having a source coupled to a drain of the first current-gain transistor and a drain of the second current-gain transistor, a gate coupled to a first DC bias voltage, and a drain coupled to a gain output of the amplifier;
a third current-gain transistor having a gate coupled to the input of the amplifier via a second gain path;
a second cascode transistor having a source coupled to a drain of the third current-gain transistor, a gate coupled to a second DC bias voltage, and a drain coupled to the gain output of the amplifier;
a first resistor coupled between the gate of the second current-gain transistor and a third DC bias voltage; and
a second resistor coupled between the gate of the third current-gain transistor and a fourth DC bias voltage,
wherein the third DC bias voltage is different from the fourth DC bias voltage.
2. The amplifier of claim 1 , wherein the first gain path comprises a first capacitor coupled between the input of the amplifier and the gate of the second current-gain transistor, and the second gain path comprises a second capacitor coupled between the input of the amplifier and the gate of the third current-gain transistor.
3. The amplifier of claim 1 , further comprising a source-follower transistor having a gate coupled to the gain output of the amplifier, and a source coupled to a driver output of the amplifier.
4. The amplifier of claim 3 , further comprising:
a feedback resistor coupled between the driver output of the amplifier and the input of the amplifier; and
an input resistor coupled to the input of the amplifier.
5. The amplifier of claim 4 , wherein the input resistor has a resistance within a range of 50Ω to 100Ω.
6. The amplifier of claim 3 , further comprising a current-bias transistor coupled to the source of the source-follower transistor, and configured to provide a bias current for the source-follower transistor.
7. The amplifier of claim 6 , wherein a source of the current-bias transistor is coupled to a source of the second current-gain transistor.
8. The amplifier of claim 6 , wherein a drain of the current-bias transistor is coupled to the source of the source-follower transistor.
9. An amplifier, comprising:
a first current-gain transistor having a gate coupled to an input of the amplifier;
a second current-gain transistor having a gate coupled to the input of the amplifier via a gain path;
a cascode transistor having a source coupled to a drain of the first current-gain transistor and a drain of the second current-gain transistor, a gate coupled to a first DC bias voltage, and a drain coupled to a gain output of the amplifier;
a source-follower transistor having a gate coupled to the gain output of the amplifier, and a source coupled to a driver output of the amplifier; and
a current-bias transistor coupled to the source of the source-follower transistor, and configured to provide a bias current for the source-follower transistor.
10. The amplifier of claim 9 , wherein the gain path comprises a capacitor coupled between the input of the amplifier and the gate of the second current-gain transistor.
11. The amplifier of claim 10 , further comprising a resistor coupled between the gate of the second current-gain transistor and a second DC bias voltage.
12. The amplifier of claim 9 , further comprising:
a feedback resistor coupled between the driver output of the amplifier and the input of the amplifier; and
an input resistor coupled to the input of the amplifier.
13. The amplifier of claim 12 , wherein the input resistor has a resistance within a range of 50Ω to 100Ω.
14. The amplifier of claim 9 , wherein a source of the current-bias transistor is coupled to a source of the second current-gain transistor.
15. An amplifier, comprising:
a first current-gain transistor having a gate coupled to an input of the amplifier;
a second current-gain transistor having a gate coupled to the input of the amplifier via a gain path;
a first cascode transistor having a source coupled to a drain of the first current-gain transistor, a gate coupled to a first DC bias voltage, and a drain coupled to a gain output of the amplifier;
a second cascode transistor having a source coupled to a drain of the second current-gain transistor, a gate coupled to a second DC bias voltage, and a drain coupled to the gain output of the amplifier;
a source-follower transistor having a gate coupled to the gain output of the amplifier, and a source coupled to a driver output of the amplifier; and
a current-bias transistor coupled to the source of the source-follower transistor, and configured to provide a bias current for the source-follower transistor.
16. The amplifier of claim 15 , wherein the gain path comprises a capacitor coupled between the input of the amplifier and the gate of the second current-gain transistor.
17. The amplifier of claim 16 , further comprising a resistor coupled between the gate of the second current-gain transistor and a third DC bias voltage.
18. The amplifier of claim 15 , further comprising:
a feedback resistor coupled between the driver output of the amplifier and the input of the amplifier; and
an input resistor coupled to the input of the amplifier.
19. The amplifier of claim 18 , wherein the input resistor has a resistance within a range of 50Ω to 100Ω.
20. The amplifier of claim 15 , wherein a source of the current-bias transistor is coupled to a source of the second current-gain transistor.