Apparatus and method for designing an architecturally homogeneous power-performance heterogeneous multicore processor using simulated annealing optimization

1. An apparatus comprising:

a first core with a first architecture and that is designed for a first voltage frequency domain; and

a second core with the first architecture and that is designed for a second voltage-frequency domain, wherein the first voltage-frequency domain and second voltage-frequency domain are calculated by selecting a set of voltage-frequency domains for a standard cell library, reducing one or more of a frequency and a voltage of each voltage-frequency domain in the set of voltage-frequency domains to synthesize synthetic voltage-frequency domains in the set of voltage-frequency domains, and calculating the first voltage-frequency domain and second voltage-frequency domain through simulated annealing minimization of an equation ΣE(F i (v))

wherein E is an energy consumption, F is a frequency in the set of voltage-frequency domains, v is a voltage in the set of voltage-frequency domains, and v and F(v) are initially set to a highest voltage-frequency domain of the standard cell library, and the simulated annealing minimization is a function of a multicore performance yield as a function of voltage Y(v) for the first core and the second core, wherein Y(v) is calculated as Y(v)=Pr1/nΣ i=1 n IPC i (u)/IPC base

where Pr is performance of the first core and the second core, IPCbase is instructions per cycle (IPC) of an application running in a core of the first and second cores with a highest voltage-frequency domain, IPCi(v) is an IPC of the application running on an i th core.

2. The apparatus of claim 1 , wherein the first core and the second core are each selected from the core type consisting of homogeneous cores with Dynamic Voltage and Frequency Scaling (D-DVFS), homogeneous cores with Static VF (SVFS), homogeneous power-performance heterogeneous cores (AHPH), and Architecturally homogeneous power-performance heterogeneous cores with task migrations (AHPH-TM).

3. The apparatus of claim 1 , wherein the set of voltage-frequency domains are synthesized for the first architecture from the standard cell library by selecting at least two frequencies that do not exceed a maximum frequency for each standard cell library voltage.

4. The apparatus of claim 3 , wherein the set voltage-frequency domains are specified.

5. The apparatus of claim 1 , further comprising an allocation module allocating a processing task at runtime to one of the first core and the second core for an epoch.

6. The apparatus of claim 5 , wherein the processing task is allocated from a higher voltage-frequency domain core to a lower voltage-frequency domain core if a utilization of the higher voltage-frequency domain core falls below a lower utilization threshold for the epoch and the processing task is allocated from the lower voltage-frequency domain core to the higher voltage-frequency domain core if a utilization of the higher voltage-frequency domain core exceeds an upper utilization threshold for the epoch.

7. The apparatus of claim 6 , wherein the utilization is selected from the group consisting of a workload, a temperature, and instructions executed per epoch.

8. The apparatus of claim 1 , wherein the first core is synthesized with the first architecture for the first voltage-frequency domain and the second core is synthesized with the first architecture for the second voltage-frequency domain.

9. A method for multicore processor design comprising:

selecting a set of voltage-frequency domains for a cell library;

synthesizing synthetic voltage-frequency domains in the set of voltage-frequency domains by reducing one or more of a frequency and a voltage of each voltage-frequency domain in the set of voltage-frequency domains;

calculating a first voltage-frequency domain for a first core with a first architecture and a second voltage-frequency domain for a second core with the first architecture through simulated annealing minimization of an equation ΣE(F i (v))

wherein E is an energy consumption, F is a frequency in the set of voltage-frequency domains, v is a voltage in the set of voltage-frequency domains, and v and F(v) are initially set to a highest voltage-frequency domain of the standard cell library, and the simulated annealing minimization is a function of a multicore performance yield as a function of voltage Y(v) for the first core and the second core, wherein Y(v) is calculated as Y(v)=Pr1/nΣ i=1 n IPC i (u)/IPC base

where Pr is performance of the first core and the second core, IPCbase is instructions per cycle (IPC) of an application running in a core of the first and second cores with a highest voltage-frequency domain, IPCi(v) is an IPC of the application running on an i th core.

10. The method of claim 9 , wherein the first core and the second core are each selected from the core type consisting of homogeneous cores with Dynamic Voltage and Frequency Scaling (D-DVFS), homogeneous cores with Static VF (SVFS), homogeneous power-performance heterogeneous cores (AHPH), and Architecturally homogeneous power-performance heterogeneous cores with task migrations (AHPH-TM).

11. The method of claim 9 , wherein a set of voltage-frequency domains are synthesized for the first architecture from a standard cell library by selecting at least two frequencies that do not exceed a maximum frequency for each standard cell library voltage.

12. The method of claim 11 , wherein the set voltage-frequency domains are specified.

13. The method of claim 9 , the method further comprising:

synthesizing the first core with the first architecture for the first voltage-frequency domain; and

synthesizing the second core with the first architecture for the second voltage-frequency domain.

14. A computer program product for multicore processor design comprising:

a non-transitory computer readable storage medium having computer readable program code embodied therein, and when executed by a processor, the computer readable program code configured to:

select a set of voltage-frequency domains for a cell library;

synthesize synthetic voltage-frequency domains in the set of voltage-frequency domains by reducing one or more of a frequency and a voltage of each voltage-frequency domain in the set of voltage-frequency domains;

calculating a first voltage-frequency domain for a first core with a first architecture and a second voltage-frequency domain for a second core with the first architecture through simulated annealing minimization of an equation ΣE(F i (v))

wherein E is an energy consumption, F is a frequency in the set of voltage-frequency domains, v is a voltage in the set of voltage-frequency domains, and v and F(v) are initially set to a highest voltage-frequency domain of the standard cell library, and the simulated annealing minimization is a function of a multicore performance yield as a function of voltage Y(v) for the first core and the second core, wherein Y(v) is calculated as

Y

⁡

(

v

)

=

Pr

⁢

1

n

⁢

∑

i

=

1

n

⁢

IPC

i

⁡

(

v

)

IPC

base

where Pr is performance of the first core and the second core, IPCbase is instructions per cycle (IPC) of an application running in a core of the first and second cores with a highest voltage-frequency domain, IPCi(v) is an IPC of the application running on an i th core.

15. The computer program product of claim 14 , the program code further configured to:

synthesize the first core with the first architecture for the first voltage-frequency domain; and

synthesize the second core with the first architecture for the second voltage-frequency domain.