Built-in-self-test using embedded memory and processor in an application specific intergrated circuit
A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implemented using a few terminals of the ASIC.
1. An integrated circuit comprising:
a first memory comprising a first set of test routines;
a processing core, wherein the processing core is configured to test a first one or more components of the integrated circuit using the first set of test routines; and
an interface,
wherein the processing core is configured to receive, via the interface and from a second memory that is external to the integrated circuit, firmware, wherein the firmware is configured to replace at least a part of the first set of test routines to generate a second set of test routines, wherein the second set of test routines is stored in the first memory, and wherein the processing core is configured to test a second one or more components of the integrated circuit using the second set of test routines.
2. The integrated circuit of claim 1 , wherein:
the processing core is configured to receive, via the interface, a control signal; and
in response to a first state of the control signal, the processing core is configured to receive the firmware.
3. The integrated circuit of claim 2 , wherein:
in response to a second state of the control signal, the processing core is configured to test the first one or more components of the integrated circuit using the first set of test routines.
4. The integrated circuit of claim 1 , wherein:
the processing core is configured to receive, via the interface, a control signal;
in response to a first state of the control signal, the processing core is configured to check, via the interface, contents of the second memory; and
based on the contents of the second memory, the processing core is configured to perform one of (i) receive, via the interface and from the second memory, the firmware, and (ii) test the first one or more components of the integrated circuit using the first set of test routines.
5. The integrated circuit of claim 4 , wherein:
based on a first word of the contents of the second memory comprising an expected value, the processing core is configured to receive, via the interface and from the second memory, the firmware.
6. The integrated circuit of claim 4 , wherein:
based on a first word of the contents of the second memory not comprising an expected value, the processing core is configured to test the first one or more components of the integrated circuit using the first set of test routines.
7. The integrated circuit of claim 1 , wherein:
prior to the processing core receiving, via the interface and from the second memory, the firmware, the processing core is configured to reset the second memory.
8. The integrated circuit of claim 1 , wherein:
the first set of test routine comprises (i) a first test routine for execution when power applied to the integrated circuit is reset, and (ii) a second test routine for execution after the first test routine.
9. The integrated circuit of claim 8 , wherein:
the processing core is configured to execute the first test routine to test the integrated circuit; and
the processing core is configured to execute the second test routine to test a memory component of the integrated circuit.
10. The integrated circuit of claim 8 , wherein:
the processing core is configured to receive, via the interface, a control signal;
in response to a first state of the control signal, the processing core is configured to execute the first test routine; and
in response to a second state of the control signal, the processing core is configured to execute the second test routine.
11. The integrated circuit of claim 1 , wherein:
the processing core is configured to output, via the interface, an output signal that indicates a result of testing the first component.
12. The integrated circuit of claim 1 , wherein the integrated circuit is an application-specific integrated circuit.
13. A method comprising:
storing, in a first memory of an integrated circuit, a first set of test routines;
testing, by a processing core of the integrated circuit, a first one or more components of the integrated circuit using the first set of test routines;
receiving, by the processing core via an interface of the integrated circuit and from a second memory that is external to the integrated circuit, firmware; and
replacing, using the firmware, at least a part of the first set of test routines to generate a second set of test routines, wherein the second set of test routines is stored in the first memory.
14. The method of claim 13 , further comprising:
testing, by the processing core of the integrated circuit, a second one or more components of the integrated circuit using the second set of test routines.
15. The method of claim 13 , further comprising:
receiving, by the processing core via the interface, a control signal,
wherein receiving the firmware comprises
in response to a first state of the control signal, receiving, by the processing core via the interface of the integrated circuit and from the second memory, the firmware.
16. The method of claim 15 , wherein testing the first one or more components of the integrated circuit using the first set of test routines comprises:
in response to a second state of the control signal, testing, by the processing core of the integrated circuit, the first one or more components of the integrated circuit using the first set of test routines.
17. The method of claim 13 , wherein receiving the firmware further comprises:
receiving, by the processing core via the interface, a control signal;
in response to a first state of the control signal, checking, by the processing core via the interface, contents of the second memory; and
based on a part of the contents of the second memory matching an expected value, receiving, by the processing core via the interface of the integrated circuit and from the second memory that is external to the integrated circuit, the firmware.
18. The method of claim 17 , wherein testing the first one or more components of the integrated circuit using the first set of test routines comprises:
based on a part of the contents of the second memory not matching an expected value, testing, by the processing core of the integrated circuit, the first one or more components of the integrated circuit using the first set of test routines.
19. The method of claim 13 , further comprising:
prior to the processing core receiving the firmware, resetting, by the processing core via the interface, the second memory.
20. The method of claim 13 , wherein:
the first set of test routine comprises (i) a first test routine for execution when power applied to the integrated circuit is reset, and (ii) a second test routine for execution after the first test routine.