Capacitor in Post-Passivation structures and methods of forming the same

1. A device comprising:

a first metal pad;

a first passivation layer comprising a portion overlapping the first metal pad, wherein the first passivation layer comprises a lower sub layer and an upper sub layer over the lower sub layer; and

a capacitor comprising:

a bottom capacitor electrode underlying the first passivation layer, wherein the bottom capacitor comprises the first metal pad;

a top capacitor electrode over the portion of the first passivation layer, wherein the top capacitor electrode penetrates through the upper sub layer of the first passivation layer to contact a top surface of the lower sub layer of the first passivation layer; and

a capacitor insulator comprising the portion of the first passivation layer.

2. The device of claim 1 further comprising:

a plurality of low-k dielectric layers underlying the first passivation layer, wherein the first passivation layer comprises a non-low-k dielectric material.

3. The device of claim 2 further comprising a second passivation layer underlying the first passivation layer and the first metal pad, wherein the second passivation layer is overlying the plurality of low-k dielectric layers, and comprises a non-low-k dielectric material.

4. The device of claim 2 , wherein the bottom capacitor electrode further comprises:

a second metal pad in a top one of the low-k dielectric layers, wherein the first metal pad overlaps the second metal pad; and

a via between and interconnecting the first metal pad and the second metal pad.

5. The device of claim 1 further comprising:

an additional metal pad level with, and formed of a same material as, the first metal pad;

a Post-Passivation Interconnect (PPI) over and connected to the additional metal pad; and

an Under-Bump Metallurgy (UBM) over and connected to the PPI.

6. The device of claim 1 further comprising:

a polymer layer over the first passivation layer; and

a Post-Passivation Interconnect (PPI) comprising a first portion over the polymer layer, and a second portion extending into the polymer layer and connected to the first portion, wherein the second portion acts as the top capacitor electrode.

7. The device of claim 1 , wherein the capacitor is located in a scribe line of a semiconductor wafer.

8. The device of claim 1 , wherein the lower sub layer and the upper sub layer of the first passivation layer comprise different materials.

9. A device comprising:

a plurality of low-k dielectric layers;

a first metal pad over the plurality of low-k dielectric layers;

a first passivation layer comprising a portion overlapping the first metal pad, wherein the passivation layer comprises a non-low-k dielectric material, and wherein the first passivation layer comprises a lower sub layer and an upper sub layer over the lower sub layer, with the lower sub layer and the upper sub layer comprising different materials;

a first polymer layer over the first passivation layer; and

a Post-Passivation Interconnect (PPI) comprising:

a first portion over the first polymer layer; and

a second portion penetrating through the first polymer layer to contact a top surface of the upper sub layer of the first passivation layer, wherein the second portion overlaps the first metal pad to form a capacitor with the first metal pad, and wherein the portion of the first passivation layer overlapping the first metal pad acts as a capacitor insulator of the capacitor.

10. The device of claim 9 , wherein the lower sub layer comprises silicon oxide, and wherein the upper layer comprises silicon nitride.

11. The device of claim 9 further comprising a second polymer layer over the first polymer layer, wherein an entirety of the PPI is covered by the second polymer layer.

12. The device of claim 9 further comprising:

a second metal pad in a top one of the low-k dielectric layer, wherein the second metal pad has a top-view size close to a top-view size of the first metal pad; and

vias between and interconnecting the first metal pad and the second metal pad.

13. The device of claim 9 , wherein the capacitor is located in a scribe line of a semiconductor wafer.

14. The device of claim 7 , wherein the capacitor is located in chip of a semiconductor wafer.

15. A device comprising:

a plurality of low-k dielectric layers;

a first metal pad over the plurality of low-k dielectric layers;

a first passivation layer comprising a portion overlapping the first metal pad, wherein the passivation layer comprises a non-low-k dielectric material, and wherein the first passivation layer comprises a lower sub layer and an upper sub layer over the lower sub layer, with the lower sub layer and the upper sub layer comprising different materials;

a first polymer layer over the first passivation layer; and

a Post-Passivation Interconnect (PPI) comprising:

a first portion over the first polymer layer; and

a second portion penetrating through the first polymer layer and the upper sub layer of the first passivation layer to contact a top surface of the lower sub layer of the first passivation layer, wherein the second portion overlaps the first metal pad to form a capacitor with the first metal pad, and wherein the portion of the first passivation layer overlapping the first metal pad acts as a capacitor insulator of the capacitor.

16. The device of claim 15 , wherein the lower sub layer comprises silicon oxide, and wherein the upper layer comprises silicon nitride.

17. The device of claim 15 further comprising a second polymer layer over the first polymer layer, wherein an entirety of the PPI is covered by the second polymer layer.

18. The device of claim 15 further comprising:

a second metal pad in a top one of the low-k dielectric layer, wherein the second metal pad has a top-view size close to a top-view size of the first metal pad; and

vias between and interconnecting the first metal pad and the second metal pad.

19. The device of claim 15 , wherein the capacitor is located in a scribe line of a semiconductor wafer.

20. The device of claim 15 , wherein the capacitor is located in chip of a semiconductor wafer.