IP Library Granted Patent US 8,889,503
Granted Patent B2
US 8,889,503 · App. 14/104,289 · Granted Nov 18, 2014

Method for manufacturing semiconductor device

Inventor: Kenji Yoneda (Kyoto, JP)
Assignee: Panasonic Corporation
H01L21/26513H01J2237/24528H01L21/26586H01L21/68771H01L29/6659H01L21/68764H01L29/045H01J2237/20207H01J2237/31701H01L29/6656
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Quick Facts
Patent No.
US 8,889,503
App. No.
14/104,289
Granted
Nov 18, 2014
Kind
B2
Abstract

Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has Off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface.

Claims (37)

1. A method for manufacturing a semiconductor device which includes, on a semiconductor substrate having a notch, a plurality of transistors in parallel with and perpendicular to a notch direction extending between a center of the semiconductor substrate and the notch, the method comprising:

preparing the semiconductor substrate which has a front surface having an Off angle of at least 2 degrees and at most 2.8 degrees from (100) plane in a direction in which a Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and

doping impurities into the front surface of the semiconductor substrate in a direction perpendicular to the front surface.

2. The method for manufacturing the semiconductor device according to claim 1 ,

wherein the Twist angle is 22.5 degrees.

3. The method for manufacturing the semiconductor device according to claim 1 ,

wherein the notch is formed at a periphery of the semiconductor substrate in <0-11> direction, and

the plurality of transistors are formed on the semiconductor substrate in the <0-11> direction and <011> direction, or in <001> direction and <010> direction.

4. The method for manufacturing the semiconductor device according to claim 1 ,

wherein the notch is formed at a periphery of the semiconductor substrate in <0-11> direction, and

the plurality of transistors are formed on the semiconductor substrate in the <0-11> direction, <011> direction, <001> direction, and <010> direction.

5. The method for manufacturing the semiconductor device according to claim 1 ,

wherein an error angle of the Off angle is within ±0.1 degree.

6. The method for manufacturing the semiconductor device according to claim 1 ,

wherein the vertical direction is a direction of 0±0.15 degree relative to the front surface of the semiconductor substrate.

7. The method for manufacturing the semiconductor device according to claim 1 ,

wherein doping the impurities is to form channel regions of the plurality of transistors.

8. The method for manufacturing the semiconductor device according to claim 1 ,

wherein doping the impurities is to form source-drain regions of the plurality of transistors.

9. The method for manufacturing the semiconductor device according to claim 1 ,

wherein doping the impurities is to form extension regions of the plurality of transistors.

10. The method for manufacturing the semiconductor device according to claim 2 ,

wherein the notch is formed at a periphery of the semiconductor substrate in <0-11> direction, and

the plurality of transistors are formed on the semiconductor substrate in the <0-11> direction and <011> direction, or in <001> direction and <010> direction.

11. The method for manufacturing the semiconductor device according to claim 2 ,

wherein the notch is formed at a periphery of the semiconductor substrate in <0-11> direction, and

the plurality of transistors are formed on the semiconductor substrate in the <0-11> direction, <011> direction, <001> direction, and <010> direction.

12. The method for manufacturing the semiconductor device according to claim 2 ,

wherein an error angle of the Off angle is within ±0.1 degree.

13. The method for manufacturing the semiconductor device according to claim 2 ,

wherein the vertical direction is a direction of 0±0.15 degree relative to the front surface of the semiconductor substrate.

14. The method for manufacturing the semiconductor device according to claim 2 ,

wherein doping the impurities is to form channel regions of the plurality of transistors.

15. The method for manufacturing the semiconductor device according to claim 2 ,

wherein doping the impurities is to form source-drain regions of the plurality of transistors.

16. The method for manufacturing the semiconductor device according to claim 2 ,

wherein doping the impurities is to form extension regions of the plurality of transistors.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2014
From: YONEDA, KENJI
To: PANASONIC CORPORATION
Reel/Frame 032318/0766 →
Priority Claims (1)
JP 2011-131684 · Jun 13, 2011 · national
Continuity (2)
Continuation PCTJP2012003792 · Jun 11, 2012
Related Publication 20140106521A1 · Apr 17, 2014