IP Library Granted Patent US 8,891,259
Granted Patent B2
US 8,891,259 · App. 13/198,981 · Granted Nov 18, 2014

Control circuit and method for audible noise suppression in a power converter

Inventors: PingAn Zhao (Shanghai, CN); Huizhen Zhu (Shanghai, CN); Hu Wang (Shanghai, CN); Chao Gao (Shanghai, CN)
Assignee: BCD Semiconductor Manufacturing Limited
H02M3/33507H02M2001/0032Y02B70/16H02M1/44
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Quick Facts
Patent No.
US 8,891,259
App. No.
13/198,981
Granted
Nov 18, 2014
Kind
B2
Abstract

A control circuit is configured for controlling a power switch to regulate an output of a power converter. The control circuit is configured to increase a switching frequency of the power switch when a first signal representing a magnitude of the power converter is below a first output level. In some embodiment, the first output level is selected such that when the first signal is below the first output level, the power converter may generate audible noise. In an embodiment, when the first signal is above the first output level, the control circuit is configured to turn off the power switch when a second signal representing a current in the power switch is above a first reference level. On the other hand, when the first signal is below the first output level, the control circuit is configured to turn off the power switch if the second signal reaches a lower reference level.

Claims (28)

1. A control circuit for controlling a power switch to regulate an output of a power converter, wherein the control circuit is configured to increase a switching frequency of the power switch when a first signal representing a magnitude of the output of the power converter is below a first output level, wherein, when the first signal representing the magnitude of the output of the power converter is above the first output level, the control circuit is configured to turn off the power switch if a second signal representing a current in the power switch is above a first reference level Vref 1 ; and

wherein, when the first signal is below the first output level, the control circuit is configured to turn off the power switch if the second signal is above a second reference level Vref 2 ;

wherein the control circuit is configured to scale the first signal according to a ratio between Vref 1 and Vref 2 based on an internal signal, which is related to a comparison between the output of the power converter and the first output level, and is used to select Vref 1 or Vref 2 .

2. The control circuit of claim 1 , wherein, the first output level is selected such that when the first signal is below the first output level, the power converter may generate audible noise.

3. The control circuit of claim 1 , further comprising a first circuit for generating a first signal representing a magnitude of the output of the power converter, the first circuit comprising:

a first terminal for receiving a feedback signal associated with the output;

a first comparator circuit for comparing the feedback signal with a feedback reference signal;

an integrator circuit coupled to the output of the first comparator circuit for generating an analog signal; and

a second comparator circuit coupled to the integrator circuit for providing the first signal representing a magnitude of the output of the power converter the second comparator circuit having:

a first terminal for receiving the analog signal 1 ; and

a second terminal for receiving a feedback signal from a voltage divider circuit that includes a first resistor and a second resistor coupled in series with a transistor controlled by a state signal which indicates that the switching frequency of the power switch needs to be raised.

4. The control circuit of claim 3 , wherein the pulsed feedback signal is provided by an auxiliary winding coupled to an output winding in the power converter.

5. The control circuit of claim 3 , wherein a ratio of the first reference level to the second reference level is equal to a ratio of (R 1 +R 2 )/R 2 , wherein R 1 is the resistance of the first resistor and R 2 is the resistance of the second resistor.

6. A control circuit for controlling a power switch to regulate an output of a power converter, wherein the control circuit is configured to increase a switching frequency of the power switch when a first signal representing a magnitude of the output of the power converter is below a first output level, wherein the first signal is scaled down in order to represent the magnitude of the output of the power converter,

wherein the control circuit is configured to increase the switching frequency of the power switch, when the first signal representing a magnitude of the output of the power converter is below the first output level and above a second output level,

wherein when the magnitude of the output of the power converter is below the first output level, the power converter is in an audible noise generation range, and the switching frequency of the power switch is increased to avoid the audible noise;

wherein when the magnitude of the output of the power converter is below the second output level, the output is so low that the audible noise becomes acceptable, and the switching frequency of the power switch is not increased so as to maintain low standby power consumption.

7. The control circuit of claim 6 , wherein, when the first signal representing the output of the power converter is above the first output level or below the second output level, the control circuit is configured to turn off the power switch if a second signal representing a current in the power switch is above a first reference level, the second output level being lower than the first output level; and

wherein, when the first signal is below the first output level and above the second output level, the control circuit is configured to turn off the power switch if the second signal is above a second reference level, the second reference level being lower than the first reference level.

8. A control circuit for controlling a power switch to regulate an output of a power converter, wherein the control circuit is configured to increase a switching frequency of the power switch when a first signal representing a magnitude of the output of the power converter is below a first output level, wherein the control circuit further comprises a first circuit for generating the first signal representing a magnitude of the output of the power converter, the first circuit including:

a first terminal for receiving a feedback signal associated with the output;

a first comparator circuit for comparing the feedback signal with a feedback reference signal;

an integrator circuit coupled to the output of the first comparator circuit for generating an analog signal; and

a second comparator circuit coupled to the integrator circuit for providing the first signal representing a magnitude of the output of the power converter the second comparator circuit having:

a first terminal for receiving the analog signal 1 ; and

a second terminal for receiving a feedback signal from a voltage divider circuit that includes a first resistor and a second resistor coupled in series with a transistor controlled by a state signal which indicates that the switching frequency of the power switch needs to be raised.

9. The control circuit of claim 8 , wherein the pulsed feedback signal is provided by an auxiliary winding coupled to an output winding in the power converter.

10. The control circuit of claim 8 , wherein a ratio of the first reference level to the second reference level is equal to a ratio of (R 1 +R 2 )/R 2 , wherein R 1 is the resistance of the first resistor and R 2 is the resistance of the second resistor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2020
From: BCD SEMICONDUCTOR MANUFACTURING LIMITED
To: BCD SHANGHAI MICRO-ELECTRONICS COMPANY LIMITED
Reel/Frame 054855/0415 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SIR NAME OF THE FIRST NAMED INVENTOR FROM ZHU TO ZHAO PREVIOUSLY RECORDED ON REEL 026708 FRAME 0838. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR'S INTEREST. Recorded Aug 10, 2011
From: ZHAO, PINGAN; ZHU, HUIZHEN; WANG, HU; GAO, CHAO
To: BCD SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 026729/0897 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2011
From: ZHU, PINGAN; ZHU, HUIZHEN; WANG, HU; GAO, CHAO
To: BCD SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 026708/0838 →
Priority Claims (1)
CN 2011 1 0128586 · May 18, 2011 · national
Continuity (1)
Related Publication 20120293146A1 · Nov 22, 2012