Low gate-leakage structure and method for gallium nitride enhancement mode transistor
The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; and a gate stack disposed on the AlGaN layer. The gate stack includes a III-V compound n-type doped layer; a III-V compound p-type doped layer adjacent the III-V compound n-type doped layer; and a metal layer formed over the III-V compound p-type doped layer and the III-V compound n-type doped layer.
1. A semiconductor structure comprising:
a gallium nitride (GaN) layer on a substrate;
an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; and
a gate stack disposed on the AlGaN layer, wherein the gate stack includes:
a pair of layers forming a diode, wherein the pair of layers includes:
a Group III-V compound n-type doped layer; and
a Group III-V compound p-type doped layer adjacent the Group III-V compound n-type doped layer;
a metal layer formed over the pair of layers; and
a first dielectric layer interposing the pair of layers and the metal layer;
wherein the Group III-V compound n-type doped layer, the Group III-V compound p-type doped layer, and the metal layer have substantially co-planar sidewalls.
2. The semiconductor structure of claim 1 , wherein the gate stack further includes a second dielectric layer underlying the metal layer and underlying the pair of layers.
3. The semiconductor structure of claim 1 , further comprising another pair of Group III-V compound doped layers.
4. The semiconductor structure of claim 1 , wherein the Group III-V compound n-type doped layer includes a n-type GaN layer and the Group III-V compound p-type doped layer includes a p-type GaN layer.
5. The semiconductor structure of claim 4 , wherein the Group III-V compound n-type doped layer is doped with an impurity selected from the group consisting of silicon and oxygen.
6. The semiconductor structure of claim 4 , wherein the Group III-V compound p-type doped layer is doped with an impurity selected from the group consisting of magnesium, calcium, zinc, beryllium, and carbon.
7. The semiconductor structure of claim 1 , wherein each of the Group III-V compound p-type doped layer and the Group III-V compound n-type doped layer has a thickness ranging between about 1 nanometer and about 100 nanometers.
8. The semiconductor structure of claim 1 , wherein the GaN layer is undoped or unintentionally doped.
9. The semiconductor structure of claim 8 , further comprising source and drain features configured with the GaN layer, the AlGaN layer, and gate stack to form an enhancement-mode transistor.
10. A semiconductor structure comprising:
a gallium nitride (GaN) layer on a substrate;
an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer;
a barrier layer disposed on the GaN layer; and
a gate stack disposed on the barrier layer, wherein the gate stack includes:
a Group III-V compound n-type doped layer;
a Group III-V compound p-type doped layer adjacent the Group III-V compound n-type doped layer;
a dielectric layer disposed on the Group III-V compound p-type doped layer; and
a metal layer formed over the Group III-V compound p-type doped layer and the Group III-V compound n-type doped layer.
11. The semiconductor structure of claim 10 , wherein the Group III-V compound p-type doped layer and the AlGaN layer form a first diode; and wherein the Group III-V compound p-type doped layer and the Group III-V compound n-type doped layer form a second diode.