Chip assembly system
An assembly of semiconductor wafers/chips wherein the adjacent surfaces of the two wafers/chips comprise an insulating layer having opposite copper pads inserted therein. The insulating layer is made of a material selected from the group including silicon nitride and silicon carbon nitride.
1. An assembly of semiconductor wafers/chips wherein the adjacent surfaces of two wafers/chips (W 1 , W 2 ) each comprise a silicon oxide layer having copper pads formed therein, wherein the silicon oxide layer is coated, outside of regions in which the copper pads are formed, with a silicon nitride or silicon carbon nitride layer thinner than the thickness of the copper pads, and wherein an external surface of the silicon nitride or silicon carbon nitride layer is substantially planar with an external surface of the pads.
2. The assembly of semiconductor wafers/chips of claim 1 , wherein the opposite surfaces of the copper pads (Pi 1 , Pi 2 ) are nitrided-silicided.
3. The assembly of semiconductor wafers/chips of claim 1 , wherein the opposite surfaces of the copper pads (Pi 1 , Pi 2 ) are coated with CoWP.
4. The assembly of semiconductor chips/wafers of claim 1 , wherein the pads are regularly distributed on each of the wafers/chips, at least some of the pads being electrically unconnected.
5. The assembly of claim 1 , wherein several first chips are associated with a same second chip.
6. The assembly of claim 5 , wherein the second chip belongs to a semiconductor wafer comprising an assembly of second chips.