Semiconductor memory device comprising inverting amplifier circuit and driving method thereof
View Patent ↗A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m.
1. A semiconductor memory device comprising:
a first bit line and a second bit line;
a first word line and a second word line;
a first memory cell and a second memory cell;
an inverting amplifier circuit configured to supply an inverted and amplified potential of the second bit line to the first bit line or an inverted and amplified potential of the first bit line to the second bit line;
a first switch provided between the first bit line and a first input terminal of the inverting amplifier circuit; and
a second switch provided between the second bit line and a second input terminal of the inverting amplifier circuit,
wherein each of the first memory cell and the second memory cell comprises a writing transistor, a reading transistor, and a capacitor comprising a first electrode and a second electrode,
wherein one of a source and a drain of the writing transistor of the first memory cell, a gate of the reading transistor of the first memory cell, and the first electrode of the capacitor of the first memory cell are connected to each other,
wherein one of a source and a drain of the writing transistor of the second memory cell, a gate of the reading transistor of the second memory cell, and the first electrode of the capacitor of the second memory cell are connected to each other,
wherein the other of the source and the drain of the writing transistor of the first memory cell is connected to the first bit line,
wherein the other of the source and the drain of the writing transistor of the second memory cell is connected to the second bit line,
wherein a gate of the writing transistor of the first memory cell is connected to the second word line,
wherein a gate of the writing transistor of the second memory cell is connected to the first word line,
wherein one of a source and a drain of the reading transistor of the first memory cell is connected to the second bit line,
wherein one of a source and a drain of the reading transistor of the second memory cell is connected to the first bit line,
wherein the second electrode of the capacitor of the first memory cell is connected to the first word line, and
wherein the second electrode of the capacitor of the second memory cell is connected to the second word line.
2. A driving method of the semiconductor memory device according to claim 1 , comprising the steps of:
pre-charging the first bit line and the second bit line to different potentials;
changing a potential of the first word line; and
outputting a potential whose phase is opposite to a phase of a potential of the second bit line to the first bit line with the inverting amplifier circuit.
3. The semiconductor memory device according to claim 1 , wherein the writing transistor and the reading transistor are provided in different layers.
4. The semiconductor memory device according to claim 1 , wherein a kind of semiconductor used in the writing transistor and a kind of semiconductor used in the reading transistor are different from each other.
5. The semiconductor memory device according to claim 1 , wherein the inverting amplifier circuit is a flip-flop circuit.
6. The semiconductor memory device according to claim 1 , wherein the inverting amplifier circuit is an inverter.