IP Library Granted Patent US 8,921,992
Granted Patent B2
US 8,921,992 · App. 13/804,902 · Granted Dec 30, 2014

Stacked wafer with coolant channels

Inventors: Christopher R. Koontz (Manhattan Beach, CA); Tse E. Wong (Los Alamitos, CA); Jason G. Milne (Hawthorne, CA)
Assignee: Raytheon Company
H01L23/46H01L21/50
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Quick Facts
Patent No.
US 8,921,992
App. No.
13/804,902
Granted
Dec 30, 2014
Kind
B2
Abstract

A wafer assembly with internal fluid channels. The assembly is fabricated by creating one or more channels in a first surface of a first semiconductor wafer and creating an oxide surface on the first surface of the first semiconductor wafer. An oxide surface is also created on a first surface of a second semiconductor wafer. The assembly is fabricated by bonding the oxide surface of the first surface of the first semiconductor wafer to the oxide surface of the first surface of the second semiconductor wafer to create a wafer assembly and to seal the one or more channels at edges defined by the bonded first and second surfaces.

Claims (15)

1. A wafer assembly with internal fluid channels, the assembly comprising:

a first semiconductor wafer having a first surface that includes a first oxide surface, wherein the first surface of the first semiconductor wafer defines one or more channels; and

a second semiconductor wafer having a first surface that includes a second oxide surface,

wherein the first oxide surface of the first surface of the first semiconductor wafer is bonded to the second oxide surface of the first surface of the second semiconductor wafer to seal the one or more channels at edges defined by the bonded first and second oxide surfaces, such that an inorganic covalent bondline is created between the first and second oxide surfaces.

2. The assembly of claim 1 , wherein the first surface of the second semiconductor wafer defines one or more channels that align with the one or more channels in the first surface of the first semiconductor wafer, and wherein the one or more aligned channels in the first semiconductor wafer and second semiconductor wafer are sealed at the edges defined by the bonded first and second oxide surfaces.

3. The assembly of claim 1 , wherein the wafer assembly is configured to produce one or more semiconductor chips, each including one or more sealed channels, when the wafer assembly is diced.

4. The assembly of claim 1 , comprising one or more vias in the first semiconductor wafer or second semiconductor wafer that are in fluid communication with the one or more channels.

5. The assembly of claim 4 , wherein each via is a conduit for inputting fluid to, or outputting fluid from, the one or more channels of the wafer assembly.

6. An assembly with internal fluid channels, the assembly comprising:

a first component having a first surface that includes a first oxide surface, wherein the first surface of the first component defines one or more channels; and

a second component having a first surface that includes a second oxide surface,

wherein the first oxide surface of the first surface of the first component is bonded to the second oxide surface of the first surface of the second component to seal the one or more channels at edges defined by the bonded first and second oxide surfaces, such that an inorganic covalent bondline is created between the first and second oxide surfaces.

7. The assembly of claim 6 , wherein the first surface of the second component defines one or more channels that align with the one or more channels in the first surface of the first component, and wherein the one or more aligned channels in the first component and second component are sealed at the edges defined by the bonded first and second oxide surfaces.

8. The assembly of claim 6 , comprising one or more vias in the first component or second component that are in fluid communication with the one or more channels.

9. The assembly of claim 8 , wherein each via is a conduit for inputting fluid to, or outputting fluid from, the one or more channels of the assembly.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2013
From: KOONTZ, CHRISTOPHER R.; WONG, TSE E.; MILNE, JASON G.
To: RAYTHEON COMPANY
Reel/Frame 030060/0964 →
Continuity (1)
Related Publication 20140264759A1 · Sep 18, 2014