Semiconductor device
Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion ( 2 ) formed on the upper surface of a semiconductor substrate ( 1 ), a passivation layer ( 3 ) so formed on the upper surface of the semiconductor substrate ( 1 ) as to overlap a part of the electrode pad portion ( 2 ) and having a first opening portion ( 3 a ) where the upper surface of the electrode pad portion ( 2 ) is exposed, a barrier metal layer ( 5 ) formed on the electrode pad portion ( 2 ), and a solder bump ( 6 ) formed on the barrier metal layer ( 5 ). The barrier metal layer ( 5 ) is formed such that an outer peripheral end ( 5 b ) lies within the first opening portion ( 3 a ) of the passivation layer ( 3 ) when viewed in plan.
1. A semiconductor chip comprising:
an electrode pad portion formed on a face of a substrate;
a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;
a barrier metal layer formed on the electrode pad portion;
a bump electrode on the barrier metal layer; and
a second protection layer covering a region on the first protection layer and a region on the electrode pad portion,
wherein the first protection layer has a step part formed therein as a result of the first protection layer overlapping the part of the electrode pad portion,
wherein the barrier metal layer has a circumferential end part thereof formed outward of the step part as seen in a plan view,
wherein the bump electrode is bonded to the barrier metal layer,
wherein the barrier metal layer is on the electrode pad portion with a peripheral part of the barrier metal layer located over the second protection layer,
wherein the second protection layer has a second opening through which the top face of the electrode pad portion is exposed and that has an opening width smaller than the first opening, and
wherein a rim part of the second protection layer defining the second opening has an inclined shape, an upper surface of the second protection layer has a curved surface along a lower surface of the barrier metal layer, and a center point of a curvature of the curved surface as seen in a sectional view is located on a first protection layer side of the curved surface.
2. The semiconductor chip according to claim 1 , wherein the first opening has an opening width of about 85 μm to about 95 mm, and wherein the second opening has an opening width of about 55 μm to about 65 mm.
3. The semiconductor chip according to claim 1 , wherein the second protection layer is formed of polyimide.
4. A semiconductor device comprising:
the semiconductor chip according to claim 1 ,
wherein the electrode pad portion is formed of a material comprising aluminum,
wherein the barrier metal layer is formed of a material comprising titanium; and
wherein the bump electrode comprises a solder bump.
5. The semiconductor device according to claim 4 , further comprising:
a printed circuit board on which the semiconductor chip is mounted.
6. The semiconductor device according to claim 5 , further comprising:
a connection pad portion provided on a face of the printed circuit board and connected to the bump electrode.
7. The semiconductor device according to claim 6 ,
wherein a gap between the semiconductor chip and the printed circuit board is filled with a resin member.
8. The semiconductor device according to claim 7 ,
wherein a gap between the semiconductor chip and the resin member is sealed with a resin sealing layer.
9. A semiconductor device comprising:
the semiconductor chip according to claim 1 ,
a printed circuit board having on a face thereof a connection pad portion which is connected to the bump electrode; and
a resin sealing layer which fixes the semiconductor chip to the printed circuit board.
10. The semiconductor device according to claim 9 , wherein the first opening has an opening width of about 85 μm to about 95 mm, and wherein the second opening has an opening width of about 55 μm to about 65 mm.
11. The semiconductor device according to claim 9 , further comprising:
the connection pad portion.
12. The semiconductor device according to claim 11 , wherein a gap between the semiconductor chip and the printed circuit board is filled with a resin member.
13. The semiconductor device according to claim 12 , wherein a gap between the semiconductor chip and the resin member is sealed with a resin sealing layer.
14. The semiconductor device according to claim 1 , wherein the bump electrode is bonded to the barrier metal layer so as to cover a side surface of the barrier metal layer in the circumferential end part thereof.
15. A semiconductor chip comprising:
an electrode pad on a surface of a substrate;
a first protection layer disposed partially on the surface of the substrate and overlapping part of the electrode pad, the first protection having a first opening;
a second protection layer covering a region on the first protection layer and a region on the electrode pad, the second protection layer having a second opening that has a width smaller than a width of the first opening;
a barrier metal layer on the electrode pad, wherein an interface between the barrier metal layer and the electrode pad is located within the first opening and within the second opening, and wherein a peripheral part of the barrier metal layer is on the second protection layer; and
a bump electrode bonded to the barrier metal layer,
wherein an upper surface of the second protection layer has a curved surface in contact with a surface of the barrier metal layer that faces toward the substrate, and a center point of a curvature of the curved surface as seen in a sectional view is located on a substrate side of the curved surface.