Packet buffering device and packet discarding method

1. A packet buffering device comprising:

a memory configured for queuing an arriving packet temporarily; and

a processor configured for:

measuring a queue length which indicates an amount of packet data held in the memory;

measuring an output rate at which packets are output from the memory, the output rate changing in time;

predicting, before queuing the arriving packet in said memory, a length of time during which the arriving packet resides in the memory based on a value obtained by dividing the queue length measured by the output rate measured;

measuring a residence time of each packet residing in said memory, and

discarding the arriving packet before queuing the arriving packet in said memory when the length of time predicted exceeds a first reference value, but when the residence time measured is less than a second reference value, said processor does not discard the packet even if the predicted length of time exceeds the first reference value.

2. A packet buffering device as claimed in claim 1 , wherein said processor is further configured for discarding said arriving packet at a rate that varies in accordance with an amount by which the length of time predicted exceeds the first reference value.

3. A packet buffering device as claimed in claim 1 , wherein said processor is further configured for notifying a source of the arriving packet of occurrence of congestion when the length of time predicted exceeds said first reference value.

4. A packet buffering device as claimed in claim 1 , wherein in the measuring of the output rate, said processor measures an amount of packets output from said memory within a period of time, and measures the output rate based on the period and on the amount of packets output during each time interval of the period.

5. A packet buffering device as claimed in claim 1 , wherein in the measuring of the output rate, said processor measures a cumulative amount of packets written to said memory when writing a packet to said memory, and measures the output rate based on a difference between the cumulative amount of packets measured at a time of previous writing and the cumulative amount of packets measured at the time of current writing and on a time interval between the time of previous writing and the time of current writing.

6. A packet buffering device as claimed in claim 1 , wherein in the measuring of the output rate, said processor measures a cumulative amount of packets read out of said memory when reading a packet from said memory, and measures the output rate based on a difference between the cumulative amount of packets measured at a time of previous reading and the cumulative amount of packets measured at the time of current reading and on a time interval between the time of previous reading and the time of current reading.

7. A packet buffering device as claimed in claim 1 , wherein in the measuring of the output rate, said processor outputs as the output rate a weighted average value taken over successively measured output rates.

8. A packet buffering device as claimed in claim 1 , wherein in the measuring of the queue length, said processor outputs as said queue length a weighted average value taken over successively measured queue lengths.

9. A packet buffering device, comprising:

a memory configured for queuing an arriving packet temporarily; and

a processor configured for:

measuring a queue length which indicates an amount of data held in said memory;

storing the queue length measured at a time of packet arrival in said memory;

measuring a residence time of each packet residing in said memory;

predicting, before queuing the arriving packet in said memory, a length of time during which the arriving packet resides in said memory based on a value obtained by multiplying a rate of change of the queue length from the time of packet arrival to a current point in time by the residence time measured at the current point in time;

measuring a residence time of each packet residing in said memory, and

discarding the arriving packet before queuing the arriving packet in said memory when the predicted length of time exceeds a first reference value, but when the residence time measured is less than a second reference value, said processor does not discard the packet even if the predicted length of time exceeds the first reference value.

10. A packet discarding method comprising:

measuring a queue length which indicates an amount of packet data held in a memory;

measuring an output rate at which packets are output from the memory, the output rate changing with time;

predicting, before queuing the arriving packet in the memory, a length of time during which an arriving packet resides in the memory based on a value obtained by dividing the queue length measured by the output rate measured;

measuring a residence time of each packet residing in said memory, and

discarding the arriving packet before queuing the arriving packet in the memory when the length of time predicted exceeds a reference value, but when the residence time measured is less than a second reference value, said processor does not discard the packet even if the predicted length of time exceeds the first reference value.

11. A packet discarding method as claimed in claim 10 , wherein when the length of time predicted for the arriving packet exceeds the reference value, a source of the arriving packet is notified of occurrence of congestion.