Sample and hold circuit with reduced noise
A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.
1. A sample and hold circuit comprising:
an amplifier that receives a signal to be sampled on a first input;
a first capacitor characterized by a first capacitance and having a first terminal connected to an output of said amplifier by a first switch;
a second capacitor characterized by a second capacitance and having a second terminal connected to said output of said amplifier by a second switch; and
a third capacitor that connects said first and second terminals, wherein
said amplifier is configured to form a capacitive transimpedance amplifier having said third capacitor as a feedback circuit when said first switch is in a non-conducting state and said second switch is in a conducting state.
2. The sample and hold circuit of claim 1 wherein said amplifier comprises an operational amplifier with an inverting input connected to said first terminal when said first switch is in said non-conducting state.
3. The sample and hold circuit of claim 1 wherein said third capacitor has a capacitance that is less than ten percent of said first capacitance.
4. The sample and hold circuit of claim 1 wherein said second capacitance is greater than said first capacitance.
5. The sample and hold circuit of claim 1 further comprising a buffer for outputting a signal related to a potential on said first capacitor.
6. A method for sampling a signal, said method comprising:
connecting said signal to first and second capacitors by closing first and second switches at the same time, respectively;
opening said first switch while leaving said second switch closed;
causing a noise signal generated by opening said first switch to be removed from said first capacitor after said first switch is opened; and
opening said second switch, wherein
said second capacitor is coupled to said first capacitor by a network that divides a noise signal generated by opening said second switch between said network and said first capacitor.
7. The method of claim 6 further comprising generating a signal having a signal value determined by a potential on said first capacitor after said first and second switches have been opened.
8. The method of claim 6 wherein said network comprises a third capacitor that is connected between said first and second capacitors, said noise signal generated by opening said first switch being transferred to a signal across said third capacitor when said first switch is open and said second switch is closed.
9. The method of claim 6 wherein said third capacitor has a capacitance that is less than ten percent of said first capacitance.
10. The method of claim 6 wherein said second capacitance is greater than said first capacitance.
11. The method of claim 6 further comprising a buffer for outputting a signal related to a potential on said first capacitor.