Software-based thread remapping for power savings
On a multi-core processor that supports simultaneous multi-threading, the power state for each logical processor is tracked. Upon indication that a logical processor is ready to transition into a deep low power state, software remapping (e.g., thread-hopping) may be performed. Accordingly, if multiple logical processors, on different cores, are in a low-power state, they are re-mapped to same core and the core is then placed into a low power state. Other embodiments are described and claimed.
1. A method comprising:
in response to an operating system power management determining to place a first thread unit of a first processor core into a deep idle state, obtaining power state of a second thread unit of the first processor core;
in response to the power state of the second thread unit of the first processor core not in the deep idle state, obtaining power states of a first thread unit and a second thread unit of a second processor core;
in response to the power state of the second thread unit of the second processor core in the deep idle state, and the first thread unit of the second processor core not in the deep idle state, swapping work from the first thread unit of the second processor core to the first thread unit of the first processor core;
after the swapping, changing the power state of the first thread unit of the second processor core to the deep idle state; and
after the changing, changing the core power state of the second processor core.
2. The method of claim 1 , wherein said swapping is performed by control software of a computing platform comprising the first and second processor cores.
3. The method of claim 2 , wherein said swapping is performed by an operating system of the computing platform.
4. The method of claim 2 , wherein said swapping comprises performing a software-based context switch.
5. The method of claim 1 , wherein said first and second processor cores reside in the same die package.
6. The method of claim 1 , wherein said swapping comprises remapping a thread identifier of the first thread unit of the second processor core to the first thread unit of the first processor core.
7. A system comprising:
a chip package comprising a first processor that includes a plurality of thread units, and a second processor that includes a plurality of thread units;
a power module that is at least communicatively coupled with the chip package to determine, in response to a determination of an operating system power management to place a first thread unit of a first processor core into a deep idle state, whether a second thread unit of the first processor core is in the deep idle state, and in response to a determination that the second thread unit of the first processor core in not in the deep idle state, determine whether a first thread unit of a second processor core is not in the deep idle state and a second thread unit of the second processor core is in the deep idle state; and
a scheduler module that is at least communicatively coupled to the chip package and the power module to respond to the responsive determination that the first thread unit of the second processor core is not in the deep idle state and the second thread unit of the second processor core is in the deep idle state, to swap work from the first thread unit of the second processor core to the first thread unit of the first processor core.
8. The system of claim 7 , wherein said power module is further to change the power state of the first thread unit of the second processor core to the deep idle state, after the scheduler module performed said swap work.
9. The system of claim 7 , wherein said power module is further to change the processor power state of the second processor core, after the power state of the first thread unit of the second processor core has been changed to the deep idle state.
10. The system of claim 7 , wherein said scheduler module and said power module are software modules.
11. The system of claim 7 , wherein the processor cores reside on the same die package.
12. The system of claim 7 , wherein said first and second processor cores are members of a processing element having an integrated memory controller.
13. A computer program product, comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method, said method comprising:
in response to an operating system power management determining to place a first thread unit of a first processor core into a deep idle state, obtaining power state of a second thread unit of a first processor core;
in response to the power state of the second thread unit of the first processor core not in the deep idle state, obtaining power states of a first thread unit and a second thread unit of a second processor core;
in response to the power state of the second thread unit of the second processor core in the deep idle state, and the first thread unit of the second processor core not in the deep idle state, swapping work from the first thread unit of the second processor core to the first thread unit of the first processor core;
after the swapping, changing the power state of the first thread unit of the first processor core to the deep idle state; and
after the changing, changing the core power state of the first processor core.
14. The product of claim 13 , wherein said swapping comprises performing a software-based context switch.
15. The product of claim 13 , wherein said first and second processor cores reside in the same die package.
16. The product of claim 13 , wherein said swapping further comprises remapping a thread identifier of the first thread unit of the second processor core to the first thread unit of the first processor core.