FinFET with bottom SiGe layer in source/drain
View Patent ↗A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
1. A FinFET, comprising:
a substrate having a major surface;
a fin structure on the substrate, the fin extending from the major surface and having a topmost surface;
a source in the fin structure, the source extending below the topmost surface of the fin;
a drain in the fin structure, the drain extending below the topmost surface of the fin;
a channel in the fin structure between the source and the drain;
a gate dielectric layer over the channel; and
a gate over the gate dielectric layer,
wherein at least one of the source and the drain includes a bottom SiGe layer.
2. The FinFET of claim 1 , further comprising a sidewall SiGe layer in the at least one of the source or the drain.
3. The FinFET of claim 1 , wherein the source and the drain include a first layer comprising SiP or SiCP, and the first layer is disposed over the bottom SiGe layer.
4. The FinFET of claim 3 , wherein a volume ratio of SiGe to SiP or SiGe to SiCP ranges from 10% to 40%.
5. The FinFET of claim 3 , wherein a phosphorus concentration of the first layer ranges from 5e20 cm −3 to 1e22 cm −3 .
6. The FinFET of claim 3 , wherein the first layer comprises SiCP and a carbon doping percentage of the first layer ranges from 0.5% to 2%.
7. The FinFET of claim 3 , wherein the source and the drain further comprises a second layer comprising SiP or SiCP, the second layer is disposed over the first layer, and the second layer has a higher phosphorus concentration than the first layer.
8. The FinFET of claim 7 , wherein the first layer has a phosphorus concentration ranging from 5e20 cm −3 to 2e21 cm −3 .
9. The FinFET of claim 7 , wherein the second layer has a phosphorus concentration ranging from 1e21 cm −3 to 1e22 cm −3 .
10. The FinFET of claim 1 , wherein a height X of the fin structure, a height Y of the source or the drain, and a height Z of the bottom SiGe layer has a relationship of Z≦Y−X.
11. The FinFET of claim 1 , further comprising spacers adjacent to the gate.
12. The FinFET of claim 11 , wherein the spacers comprise SiN, SiCN, or SiCON.
13. A method for fonning a FinFET, comprising:
forming a fin structure extending from and above a major surface of a substrate;
recessing a source region into the fin and a drain region into the fin;
forming a source and a drain in the fin, wherein at least one of the source and the drain includes a bottom SiGe layer formed in a bottom portion of the source region or the drain region;
forming a gate dielectric layer over a channel between the source and the drain; and
forming a gate over the gate dielectric layer.
14. The method of claim 13 , wherein forming the source and the drain includes forming a sidewall SiGe layer in the at least one of the source or the drain.
15. The method of claim 13 , wherein forming the source and the drain comprises forming a first layer comprising SiP or SiCP, and the first layer is disposed over the bottom SiGe layer.
16. The method of claim 15 , wherein a phosphorus concentration of the first layer ranges from 5e20 cm −3 to 1e22 cm −3 .
17. The method of claim 15 , wherein forming the source and the drain further comprises forming a second layer over the first layer, the second layer comprises SiP or SiCP, and the second layer has a higher phosphorus concentration than the first layer.
18. The method of claim 17 , wherein the first layer has a phosphorus concentration ranging from 5e20 cm −3 to 2e21 cm −3 and the second layer has a phosphorus concentration ranging from 1e21 cm −3 to 1e22 cm −3 .
19. The method of claim 13 , further comprising forming spacers adjacent to the gate.
20. A FinFET, comprising:
a substrate;
a fin structure on the substrate;
a source in the fin structure;
a drain in the fin structure;
a channel in the fin structure between the source and the drain;
a gate dielectric layer over the channel; and
a gate over the gate dielectric layer,
wherein at least one of the source and the drain includes a top layer comprising SiP or SiCP, a bottom SiGe layer, and a sidewall SiGe layer.