Performance of off-chip connection for power amplifier
There is provided an integrated circuit comprising a main push-pull amplifier ( 108, 110 ) with balanced outputs and an additional push-pull amplifier ( 862, 863 ) with balanced outputs. Each of these balanced outputs is connected to an off-chip load ( 822 ) via respective bonding wires ( 818, 828, 830, 880 ) to provide a combined amplified signal to the load. The additional amplifier serves to compensate for crossover distortions generated by the main amplifier.
1. An amplifier arrangement provided on an integrated circuit comprising:
a main push-pull amplifier connected to receive an input signal and generate an amplified version of the input signal; and
an additional amplifier connected to receive the input signal and generate an amplified version thereof; and
wherein the outputs of the main amplifier and the additional amplifier are combined to provide an amplified output; and
wherein during operation when the bandwidth of the main amplifier is reduced, the bandwidth of the additional amplifier is maintained at a level corresponding to the bandwidth of the main amplifier before the bandwidth of the main amplifier was reduced.
2. The amplifier arrangement of claim 1 , wherein the main amplifier comprising a push-pull amplifier has a pair of outputs for connection to a respective pair of bond wires.
3. The amplifier arrangement of claim 2 , wherein during operation in a crossover region of the main amplifier, the bandwidth of the additional amplifier is greater than the bandwidth of the main amplifier.
4. The amplifier arrangement of claim 3 , wherein during operation in the crossover region of the main amplifier, the bandwidth of the main amplifier is reduced compared to the bandwidth of the main amplifier during operation outside the crossover region.
5. The amplifier of claim 2 , wherein during operation when the bandwidth of the main amplifier is reduced, the bandwidth of the additional amplifier is greater than the bandwidth of the main amplifier.
6. The amplifier of claim 2 , wherein the bias current of the main amplifier is set in dependence on a level of bias current required to provide a required bandwidth outside a crossover region of operation.
7. The amplifier of claim 2 , wherein the bias current of the main amplifier is set in dependence on a level of bias current to achieve a desired bandwidth of operation with an output transistor of the push or pull side of the amplifier fully turned on.
8. The amplifier arrangement of claim 1 , further comprising a high pass filter connected to receive the input signal and provide a high pass filtered version of the input signal as the input to the additional amplifier.
9. The amplifier arrangement of claim 1 , wherein the additional amplifier increases the overall bandwidth of the amplifier arrangement, during a period in which the bandwidth of the main amplifier is reduced, such that the phase shift between the input and the output is reduced relative to the phase shift between the input and output of the main amplifier.
10. The amplifier arrangement of claim 1 , wherein the additional amplifier increases the overall bandwidth of the amplifier arrangement, during a period in which the bandwidth of the main amplifier is reduced, such that the bandwidth of the main amplifier is reduced relative to the bandwidth of the main amplifier without the additional amplifier, wherein the bias current of the main amplifier is reduced relative to the bias current of the main amplifier without the additional amplifier.
11. The amplifier arrangement of claim 1 , wherein the main amplifier is a power amplifier.
12. The amplifier arrangement of claim 1 , wherein the main amplifier comprises a current mirror arrangement for driving an output transistor.
13. A method of amplifying an input signal comprising:
amplifying, on an integrated circuit, the input signal in a main amplifier to generate an amplified version of the input signal;
amplifying, on the integrated circuit, the input signal in an additional amplifier to generate an amplified version thereof, wherein during operation when the bandwidth of the main amplifier is reduced, the bandwidth of the additional amplifier is maintained at a level corresponding to the bandwidth of the main amplifier before the bandwidth of the main amplifier was reduced; and
combining the amplified versions of the input signal off-chip to provide an amplified output.
14. The method of claim 13 , further comprising the step of providing a bias current for the main amplifier determined in dependence on a predetermined bandwidth of operation of the main amplifier.
15. The method of claim 14 , wherein in any region of operation of the main amplifier, for the determined bias current, where the bandwidth of operation of the main amplifier is reduced, the bandwidth of operation of the additional amplifier provides for full bandwidth operation.
16. The method of claim 14 further comprising a bias current for the additional amplifier which is less than the bias current for the main amplifier, determined in dependence on a predetermined bandwidth of operation for the additional amplifier which corresponds to the bandwidth of operation of the main amplifier.
17. The method of claim 14 , wherein the bias current of the main amplifier is reduced compared to the bias current required for the main amplifier if the additional amplifier was not provided.
18. The method of claim 14 , wherein the main amplifier is a push-pull amplifier including complementary output transistors, wherein the bias current is determined in dependence on the bias current required to achieve the predetermined bandwidth with either output transistor turned on.
19. The method of claim 14 further comprising the step of high pass filtering the input signal before applying to the input of the additional amplifier.
20. The amplifier arrangement of claim 2 further comprising connecting the output of the additional amplifier to a further bond wire, and connecting the bond wired off-chip.