Nonvolatile memory, electronic apparatus, and verification method
A gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to a memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to a reference cell array is included. An electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line.
1. A nonvolatile memory comprising:
a memory cell array having a first bit line connected to N memory cells;
a reference cell array having a second bit line connected to M reference cells, the M being smaller than the N;
a comparator which compares a first electric current which flows along the first bit line with a second electric current which flows along the second bit line; and
a gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in the N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in the M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to the memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to the reference cell array,
wherein an electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line.
2. The nonvolatile memory according to claim 1 , wherein the third gate voltage is between the first gate voltage and the second gate voltage.
3. The nonvolatile memory according to claim 1 , wherein:
the reference cells are n-channel cells; and
the third gate voltage is higher than the second gate voltage.
4. The nonvolatile memory according to claim 3 , wherein:
the second non-selected word line is connected to a non-selected reference cell connected to the second bit line; and
the third gate voltage is lower than the first gate voltage.
5. The nonvolatile memory according to claim 4 , wherein threshold voltage for the non-selected reference cell connected to the second bit line is equal to threshold voltage for the first reference cell.
6. The nonvolatile memory according to claim 3 , wherein:
the second non-selected word line is connected to a second reference cell which is included in the M reference cells and which is connected to a third bit line;
fourth gate voltage is supplied to the second reference cell selected at verify time different from the erase verify time;
the third gate voltage is lower than the fourth gate voltage; and
the third bit line is connected to the second bit line at the erase verify time.
7. An electronic apparatus comprising:
a nonvolatile memory; and
a processor which controls the nonvolatile memory,
wherein:
the nonvolatile memory includes
a memory cell array having a first bit line connected to N memory cells;
a reference cell array having a second bit line connected to M reference cells, the M being smaller than the N;
a comparator which compares a first electric current which flows along the first bit line with a second electric current which flows along the second bit line; and
a gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in the N memory cells is connected, which supplies the first gate voltage at erase verify time to a second selected word line to which a first reference cell included in the M reference cells is connected, which supplies second gate voltage at erase verify time to a first non-selected word line connected to the memory cell array, and which supplies third gate voltage at erase verify time to a second non-selected word line connected to the reference cell array; and
an electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line.
8. A verification method for verifying a state of a memory cell included in a nonvolatile memory including a memory cell array having a first bit line connected to N memory cells and a reference cell array having a second bit line connected to M reference cells, the M being smaller than the N, the method comprising:
comparing, by a comparator, a first electric current which flows along the first bit line with a second electric current which flows along the second bit line; and
supplying, by a gate voltage generator, first gate voltage at erase verify time to a first selected word line to which a first memory cell included in the N memory cells is connected, supplying, by the gate voltage generator, the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in the M reference cells is connected, supplying, by the gate voltage generator, second gate voltage at the erase verify time to a first non-selected word line connected to the memory cell array, and supplying, by the gate voltage generator, third gate voltage at the erase verify time to a second non-selected word line connected to the reference cell array,
wherein an electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line.