Embedded semiconductive chips in reconstituted wafers, and systems containing same
A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
1. A process of forming a multi-chip package from a reconstituted wafer, comprising:
adhering a plurality of semiconductive dice onto a backing plate, wherein each of the plurality of semiconductive dice includes terminals disposed on an active surface thereof and a backside surface;
embedding the plurality of semiconductive dice into a rigid mass to obscure the terminals;
removing a portion of the rigid mass to expose the terminals and to form a planar exposure and a reconstituted wafer;
removing the backing plate to expose at least one backside surface;
forming a bumpless build-up layer (BBUL) above and on the planar exposure; and
coupling at least one device to the BBUL, wherein the BBUL forms an electrical connection between the at least one device and at least one of the plurality of semiconductor dice.
2. The process of claim 1 , wherein removing a portion of the rigid mass to expose the terminals is done by grinding to form the planar exposure.
3. The process of claim 1 , wherein removing a portion of the rigid mass to expose the terminals is done by polishing to form the planar exposure.
4. The process of claim 1 , wherein removing a portion of the rigid mass to expose the terminals is done by grinding followed by polishing to form the planar exposure.
5. The process of claim 1 , wherein the rigid mass is an epoxy material, the method further including removing the backing plate to expose at least one die backside surface.
6. The process of claim 1 , wherein coupling at least one device to the BBUL comprised coupling at least one active device to the BBUL.
7. The process of claim 1 , wherein coupling at least one device to the BBUL comprised coupling at least one passive device to the BBUL.
8. The process of claim 1 wherein the reconstituted wafer includes an array of apparatus.
9. The process of claim 8 , further including separating one apparatus from the reconstituted wafer.
10. The process of claim 9 wherein separating one apparatus from the reconstituted wafer occurs prior to coupling at least one device to the BBUL.
11. The process of claim 9 , further including installing the one apparatus into a computing system.
12. An apparatus comprising:
a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface;
a plurality of semiconductor dice embedded in the rigid mass, wherein the first die has an active surface and a backside surface, wherein a portion of the rigid mass extends over the plurality of semiconductor dice active surfaces, and wherein at least one of the plurality of semiconductor dice has a terminal which extends above the first die active surface that is exposed through and coplanar with the rigid mass flat surface;
wherein at least one of the plurality of semiconductor dice backside surface is coplanar with the rigid mass base surface, and wherein the rigid mass and the plurality of semiconductor dice are part of a reconstituted wafer;
a bumpless build-up layer (BBUL) structure disposed above and on the flat surface, wherein the BBUL structure is coupled to at least one of the plurality of semiconductor dice; and
at least one device coupled to the BBUL, wherein the BBUL forms an electrical connection between the at least one device and at least one of the plurality of semiconductor dice.
13. The apparatus of claim 12 , wherein at least one device coupled to the BBUL comprises at least one active device coupled to the BBUL.
14. The apparatus of claim 12 , wherein at least one device coupled to the BBUL comprised at least one passive device coupled to the BBUL.
15. The apparatus of claim 12 , wherein the apparatus is one in an array disposed in a reconstituted wafer, and wherein the rigid mass is common to each apparatus of the array.
16. A computing system comprising:
a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface;
a plurality of semiconductor dice embedded in the rigid mass, wherein the first die has an active surface and a backside surface, wherein a portion of the rigid mass extends over the plurality of semiconductor dice active surfaces, and wherein at least one of the plurality of semiconductor dice has a terminal which extends above the first die active surface that is exposed through and coplanar with the rigid mass flat surface;
wherein at least one of the plurality of semiconductor dice backside surface is coplanar with the rigid mass base surface, and wherein the rigid mass and the plurality of semiconductor dice are part of a reconstituted wafer;
a bumpless build-up layer (BBUL) structure disposed above and on the flat surface, wherein the BBUL structure is coupled to at least one of the plurality of semiconductor dice;
at least one device coupled to the BBUL, wherein the BBUL forms an electrical connection between the at least one device and at least one of the plurality of semiconductor dice; and
a substrate in contact with the base surface.
17. The computing system of claim 16 , wherein at least one device coupled to the BBUL comprises at least one active device coupled to the BBUL.
18. The computing system of claim 16 , wherein at least one device coupled to the BBUL comprised at least one passive device coupled to the BBUL.
19. The computing system of claim 16 , wherein the computing system is part of one of a cellular telephone, a pager, a portable computer, a desktop computer, and a two-way radio.