Single poly plate low on resistance extended drain metal oxide semiconductor device
A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer.
1. A semiconductor device comprising:
a substrate;
a well disposed in the substrate;
a doped shallow drain implant disposed in the well substantially across a drift region;
a conductive layer separated from the substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer; and
a high temperature oxide (HTO) layer disposed substantially across the thick/thin oxide layer.
2. The semiconductor device of claim 1 , wherein a thickness of the thin oxide layer is less than a thickness of the thick/thin oxide layer.
3. The semiconductor device of claim 2 , wherein the thickness of the thin oxide layer is from about 30 Å to about 180 Å and the thickness of the thick/thin oxide layer is from about 120 Å to about 1100 Å.
4. The semiconductor device of claim 1 , wherein the semiconductor device is an extended drain n-channel metal oxide semiconductor (ED-NMOS) device, the well is a p well (PW), and the doped shallow drain implant is an n doped shallow drain (NDD) implant.
5. The semiconductor device of claim 4 , wherein a concentration of a dopant in the NDD implant is from about 5×10 12 atoms/cm 2 to about 1×10 14 atoms/cm 2 .
6. The semiconductor device of claim 5 , wherein a slope of a channel current (I ds ) versus a channel voltage (V ds ) as the ED-NMOS device transitions from a linear response to saturation is at least about 6×10 −5 A/μm-V.
7. The semiconductor of claim 4 additionally comprising an n-type well deep (NWD) implant disposed in the substrate, wherein the PW is disposed in the NWD implant.
8. The semiconductor device of claim 4 , additionally comprising:
a source region having a source side n+ doped region disposed in the PW and a source side p+ doped region disposed in the PW;
a channel region defined by the source region and the drift region; and
a drain region having a drain side n+ doped region disposed in the NDD implant, the drain region adjacent to the drift region at a side opposite the channel region.
9. The semiconductor device of claim 8 , wherein the source side p+ doped region is a square p+ doped region having a plurality of p+ squares surrounded by the source side n+ doped region.
10. The semiconductor device of claim 8 , additionally comprising an n-channel threshold voltage adjust implant disposed in at least a portion of the NDD implant proximate to a surface of the substrate.
11. The semiconductor device of claim 8 additionally comprising a plurality of isolation structures, wherein a first isolation structure of the plurality of isolation structures is adjacent to the source region at a side opposite the channel region, and a second isolation structure of the plurality of isolation structures adjacent to the drain region at another side opposite the drift region.
12. The semiconductor device of claim 11 , wherein a third isolation structure of the plurality of isolation structures is defined by a gate region and the drain region and is substantially aligned with the drift region.
13. The semiconductor device of claim 11 , wherein the plurality of isolation structures may be any one of a field oxide layer, a shallow trench isolation structure, and any combination thereof.
14. The semiconductor device of claim 8 additionally comprising a p drift implant disposed in the NDD implant.
15. The semiconductor device of claim 14 , wherein the source side p+ doped region is a square p+ doped region having a plurality of p+ squares surrounded by the source side n+ doped region and none of the plurality of p+ squares is aligned with the p drift implant.