IP Library Granted Patent US 8,971,675
Granted Patent B2
US 8,971,675 · App. 13/073,922 · Granted Mar 3, 2015

Interconnect structure for MEMS device

Inventor: Jon Bradley Lasiter (Stockton, CA)
Assignee: QUALCOMM MEMS Technologies, Inc.
G02B26/001
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Quick Facts
Patent No.
US 8,971,675
App. No.
13/073,922
Granted
Mar 3, 2015
Kind
B2
Abstract

An interferometric modulator array is formed with connectors and/or an encapsulation layer with electrical connections. The encapsulation layer hermetically seals the array. Circuitry may also be formed over the array.

Claims (26)

1. A method of manufacturing a display device, comprising:

providing a transmissive substrate;

forming a plurality of individually addressable interferometric light modulators on the substrate, wherein forming each of the interferometric light modulators includes

forming a partially reflective optical stack on the substrate, the optical stack including a first electrode;

depositing a sacrificial layer over the optical stack;

forming a reflective layer over the sacrificial layer, the reflective layer including a second electrode;

removing the sacrificial layer to form an interferometric cavity between the optical stack and the reflective layer, wherein upon removing the sacrificial layer the reflective layer becomes movable through the cavity such that the reflective layer can be moved to an actuated position and to an unactuated position based on a voltage applied between the optical stack and reflective layer;

forming a conductive interconnect layer over the reflective layer and electrically connected to a portion of the reflective layer;

forming active circuitry including at least one of a diode, a transistor, and a zener diode connected to the interconnect layer; and

forming a conductive connector connected on one end to the active circuitry and configured to connect to an external device to control said modulator through said connector, wherein the active circuitry is connected to the connector and disposed between the interconnect and the connector.

2. The method of claim 1 , further comprising forming a via connecting the reflective layer to the interconnect.

3. The method of claim 1 , further comprising forming an encapsulation layer above the reflective layer, hermetically sealing the display device.

4. The method of claim 1 , wherein the plurality of modulators comprise at least 90 percent of the interferometric modulators in an array of interferometric modulators.

5. The method of claim 1 , wherein the connectors of the plurality of modulators collectively comprise a plurality of connector bumps.

6. The method of claim 4 , wherein the connector bumps are arranged with a pitch between about 40 microns and about 60 microns.

7. The method of claim 1 , further comprising forming a plurality of posts that support the reflective layer.

8. The method of claim 1 , wherein each modulator is characterized by at least two states and wherein the connector is configured to conduct a signal to control the state of the modulator associated with the connector.

9. The method of claim 1 , further comprising:

providing a display comprising the display device;

providing a processor that is configured to communicate with said display, said processor being configured to process image data; and

providing a memory device that is configured to communicate with said processor.

10. The method of claim 9 , further comprising electrically connecting a driver circuit to the first electrode and the second electrode, the driver circuit configured to send at least one signal to the display.

11. The method of claim 9 , further comprising a providing a controller configured to send at least a portion of the image data to the driver circuit.

12. The method of claim 9 , further comprising providing an image source module configured to send said image data to said processor.

13. The method of claim 12 , wherein the image source module comprises at least one of a receiver, transceiver, and transmitter.

14. The method of claim 9 , further comprising providing an input device configured to receive input data and to communicate said input data to said processor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2016
From: QUALCOMM MEMS TECHNOLOGIES, INC.
To: SNAPTRACK, INC.
Reel/Frame 039891/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2011
From: LASITER, JON BRADLEY
To: QUALCOMM MEMS TECHNOLOGIES, INC.
Reel/Frame 026134/0006 →
Continuity (2)
Continuation 11331705 · Jan 13, 2006
Related Publication 20110177745A1 · Jul 21, 2011