Microprocessor systems and methods for latency tolerance execution
View Patent ↗An instruction unit provides instructions for execution by a processor. A decode unit decodes instructions received from the instruction unit. Queues are coupled to receive instructions from the decode unit. Each instruction in a same queue is executed in order by a corresponding execution unit. An arbiter is coupled to each queue and to the execution unit that executes instructions of a first instruction type. The arbiter selects a next instruction of the first instruction type from a bottom entry of the queue for execution by the first execution unit.
1. A processor comprising:
an instruction unit which provides instructions for execution by the processor;
a decode unit which decodes instructions received from the instruction unit;
a plurality of execution units;
a plurality of queues, each coupled to receive instructions from the decode unit, wherein each instruction in a same queue of the plurality of queues is executed in order, and wherein each instruction in the same queue is executed by a corresponding execution unit of the plurality of execution units; and
a first arbiter coupled to each of the plurality of queues and to a first execution unit of the plurality of execution units, wherein the first execution unit executes instructions of a first instruction type, wherein the first arbiter selects a next instruction of the first instruction type from a bottom entry of a first queue of the plurality of queues for execution by the first execution unit, and further wherein the decode unit, in response to receiving a complex instruction from the instruction unit, separates the complex instruction into a first micro-instruction and a second micro-instruction which together perform the complex instruction, wherein the first micro-instruction is saved to a first selected queue of the plurality of queues, the second micro-instruction is saved to a second selected queue of the plurality of queues, and the first selected queue is different from the second selected queue.
2. The processor of claim 1 , wherein the decode unit, in response to receiving a first instruction from the instruction unit, decodes the first instruction to determine operands of the first instruction, wherein the first instruction is saved to a selected queue of the plurality of queues when the operands of the first instruction include a dependency on a second instruction already present in the selected queue.
3. A processor comprising:
an instruction unit which provides instructions for execution by the processor;
a decode unit which decodes instructions received from the instruction unit;
a plurality of execution units;
a plurality of queues, each coupled to receive instructions from the decode unit, wherein each instruction in a same queue of the plurality of queues is executed in order, and wherein each instruction in the same queue is executed by a corresponding execution unit of the plurality of execution units;
a first arbiter coupled to each of the plurality of queues and to a first execution unit of the plurality of execution units, wherein the first execution unit executes instructions of a first instruction type, the first arbiter selects a next instruction of the first instruction type from a bottom entry of a first queue of the plurality of queues for execution by the first execution unit, and the decode unit, in response to receiving a first instruction from the instruction unit, decodes the first instruction to determine operands of the first instruction, further wherein the first instruction is saved to a selected queue of the plurality of queues when the operands of the first instruction include a dependency on a second instruction already present in the selected queue; and
a register file coupled to the first execution unit, wherein when the first instruction is saved to the selected queue, a dependency indicator for each corresponding operand of the first instruction is stored to indicate whether or not the corresponding operand depends on the second instruction, which is an immediately preceding instruction within the selected queue, wherein:
when the dependency indicator for the corresponding operand indicates that it does depend on the second instruction, the second execution unit feed forwards resulting data for the corresponding operand for use in executing the first instruction, and
when the dependency indicator for the corresponding operand indicates that it does not depend on the second instruction, the first execution unit obtains data from the register file for the corresponding operand for use in executing the first instruction.
4. The processor of claim 1 , wherein the next instruction of the first instruction type selected by the arbiter results in an out of order execution.
5. A processor comprising:
an instruction unit which provides instructions for execution by the processor;
a decode unit which decodes instructions received from the instruction unit;
a plurality of execution units;
a plurality of queues, each coupled to receive instructions from the decode unit, wherein each instruction in a same queue of the plurality of queues is executed in order, and wherein each instruction in the same queue is executed by a corresponding execution unit of the plurality of execution units;
a first arbiter coupled to each of the plurality of queues and to a first execution unit of the plurality of execution units, wherein the first execution unit executes instructions of a first instruction type, wherein the first arbiter selects a next instruction of the first instruction type from a bottom entry of a first queue of the plurality of queues for execution by the first execution unit; and
a common extended queue which is configured to store additional instructions for each queue of the plurality of queues that is full.
6. A processor comprising:
an instruction unit which provides instructions for execution by the processor;
a decode unit which decodes instructions received from the instruction unit;
a plurality of execution units;
a plurality of queues, each coupled to receive instructions from the decode unit, wherein each instruction in a same queue of the plurality of queues is executed in order, and wherein each instruction in the same queue is executed by a corresponding execution unit of the plurality of execution units;
a first arbiter coupled to each of the plurality of queues and to a first execution unit of the plurality of execution units, wherein the first execution unit executes instructions of a first instruction type, wherein the first arbiter selects a next instruction of the first instruction type from a bottom entry of a first queue of the plurality of queues for execution by the first execution unit; and
a second arbiter coupled to each of the plurality of queues and to a second execution unit of the plurality of execution units, wherein the second execution unit executes instructions of a second instruction type, wherein the second arbiter selects a next instruction of the second instruction type from a bottom entry of a second queue of the plurality of queues for execution by the second execution unit.
7. A processor comprising:
an instruction unit which provides instructions for execution by the processor;
a decode unit which decodes instructions received from the instruction unit;
a register file;
a load/store execution unit;
a plurality of load queues, each coupled to receive instructions from the decode unit; and
a load arbiter coupled to each of the plurality of load queues, the register file, and the load/store execution unit, wherein the load arbiter selects a load instruction from a bottom entry of a first load queue of the plurality of load queues to provide to the load/store execution unit;
wherein after the selected load instruction is provided to the load/store execution unit, the selected load instruction remains in the bottom entry of the first load queue until an indicator is received indicating that data for the selected load instruction will be received in a subsequent clock cycle.
8. The processor of claim 7 , wherein the decode unit, in response to receiving a first instruction from the instruction unit, decodes the first instruction to determine operands of the first instruction, wherein the first instruction is saved to a selected execution queue of the plurality of execution queues when the operands of the first instruction include a dependency on a second instruction already present in the selected execution queue.
9. The processor of claim 8 , wherein when the first instruction is saved to the selected execution queue, a dependency indicator for each corresponding operand of the first instruction is stored to indicate whether or not the corresponding operand depends on the second instruction, wherein:
when the first instruction is selected for execution by an execution unit and the dependency indicator for the corresponding operand indicates that it does depend on the second instruction, the execution unit feed forwards data for the corresponding operand of the second instruction for use in executing the first instruction, and
when the first instruction is selected for execution by the execution unit and the dependency indicator for the corresponding operand indicates that it does not depend on the second instruction, the execution unit obtains data from the register file for the corresponding operand for use in executing the first instruction.
10. The processor of claim 7 , further comprising a common extended queue which is configured to store additional instructions for each load queue of the plurality of load queues that is full, wherein each instruction stored in the common extended queue has a corresponding load queue identifier which identifies a load queue of the plurality of load queues to which the instruction belongs.
11. The processor of claim 7 , wherein in response to the decode unit decoding a first instruction as a load instruction, the first instruction is saved to an empty load queue of the plurality of load queues, wherein the first instruction is saved as a first micro operation in a first entry of the empty load queue and a second micro operation in an immediately subsequent second entry of the empty load queue.
12. The processor of claim 11 , wherein each instruction stored in each queue of the plurality of load queues has a corresponding pending indicator which indicates whether the instruction is available for selection by the load arbiter when the instruction appears in a bottom entry of a load queue, and wherein:
a first pending indicator corresponding to the first micro operation is set to indicate it is available for selection by the load arbiter, and
a second pending indicator corresponding to the second micro operation is set to indicate it is not available for selection by the arbiter.
13. The processor of claim 12 , wherein the second micro operation remains in a bottom entry of a load queue until an indicator is received indicating that data for the first instruction will be received in a subsequent clock cycle.
14. The processor of claim 7 , wherein each instruction stored in the plurality of load queues has a corresponding pending indicator, and the pending indicator is set for a second micro-operation of a load instruction.
15. In a processor having a decode unit, a plurality of load queues coupled to the decode unit, an integer queue, a complex instruction queue coupled to the decode unit, and a load arbiter coupled to the plurality of load queues, a method comprising:
receiving a first instruction;
decoding the first instruction by a decode unit to determine an instruction type of the first instruction and operands of the first instruction;
for the first instruction, the method further comprises:
determining whether at least one operand of the first instruction includes a dependency on any instruction stored within any of a plurality of execution queues;
when the at least one operand of the first instruction includes the dependency, selecting a second execution queue of the plurality of execution queues which includes a second instruction on which the at least one operand depends and storing the first instruction to the second execution queue;
wherein when the first instruction is not a load instruction and the second load queue is full, storing the first instruction to the second load queue comprises:
storing the first instruction into an entry of the common extended queue, and
storing a load queue identifier in the entry of the common extended queue which identifies the selected load queue; and
when there is no operand dependency and the first instruction is a load instruction, selecting a first load queue from the plurality of load queues that is empty and storing the first instruction to the first load queue.
16. The method of claim 15 , wherein the processor further comprises, and wherein when the first instruction is not a load instruction, the method further comprises:
when the at least one operand of the first instruction does not include the dependency, selecting one of the integer queue or the complex instruction queue based on an instruction type of the first instruction and storing the first instruction to the selected queue.
17. The method of claim 15 , wherein storing the first instruction to the first load queue when the first instruction is a load instruction comprises:
storing a first micro operation of the first instruction in a first entry of the first load queue and storing a first pending indicator in the first entry which indicates that the first micro operation is available for selection by the load arbiter when the first micro operation appears in a bottom entry of the first load queue; and
storing a second micro operation of the first instruction into a second entry subsequent to the first entry of the first load queue and storing a second pending indicator in the second entry which indicates that the second micro operation is not available for selection by the load arbiter when the second micro operation appears in the bottom entry of the first load queue.
18. The method of claim 15 , wherein the selecting the second load queue of the plurality of load queues which includes the second instruction is further characterized in that the second instruction has a longer latency than a third instruction on which the at least one operand also depends, wherein the third instruction is stored in a different load queue than the second load queue.