Serial replication of multicast packets
Disclosed are various embodiments that provide serial replication of multicast packets by performing a first data fetch to fetch first data from a memory buffer, the first data comprising a first packet pointer representing a first packet and a replication number indication a number of times the first packet is to be replicated. Furthermore, various embodiments are directed to performing a second data fetch to fetch second data from a memory buffer, the second data comprising a first packet pointer representing a second packet and serially replicating the first packet and the second packet based at least in part upon the replication number and a predetermined threshold value.
1. A system comprising:
a memory buffer; and
processing circuitry configured to:
store in the memory buffer a first packet pointer, the first packet pointer representing a first packet;
store in the memory buffer a first replication number, the first replication number indicating a number of times the first packet is to be replicated;
store in the memory buffer a second packet pointer, the second packet pointer representing the second packet;
store in the memory buffer a second replication number, the second replication number indicating a number of times the second packet is to be replicated;
serially replicate the first packet during a clock cycle according to the first packet pointer to generate at least one first replicated packet;
serially replicate the second packet, during the clock cycle, based at least upon the second packet pointer, if the first replication number falls below a predetermined threshold value.
2. The processing circuitry of claim 1 , wherein the processing circuitry is further configured to store in the memory buffer, a vector bitmap, the vector bitmap indicating which ones of a plurality of output ports are scheduled to receive the at least one first replicated packet.
3. The processing circuitry of claim 2 , wherein the vector bitmap expresses a total number of replications, the total number of replications indicating a total number of times the first packet is to be replicated.
4. The processing circuitry of claim 3 , wherein the first replication number is a remaining number of replications, the remaining number of replications being less than the total number of replications.
5. The processing circuitry of claim 1 , wherein the processing circuitry is further configured to schedule writing the first packet pointer and second packet pointer to the memory buffer based at least upon a prioritization of the first packet and the second packet.
6. The processing circuitry of claim 1 , wherein the processing circuitry is further configured to refrain from serially replicating the second packet if the first replication number exceeds the predetermined threshold value.
7. The processing circuitry of claim 1 , wherein the at least one first replicated packet comprises a plurality of first replicated packets, and the processing circuitry is further configured to:
store in the memory buffer, a vector bitmap, the vector bitmap indicating which ones of a plurality of output ports are scheduled to receive respective ones of the plurality of first replicated packets;
serially replicate the first packet during the clock cycle to generate the plurality of first replicated packets; and
send the plurality of first replicated packets to a subset of output ports according to the vector bitmap which ones of a plurality of output ports are scheduled to receive the at least one first replicated packet.
8. A method comprising:
performing a first data fetch to fetch first data from a memory buffer, the first data comprising a first packet pointer representing a first packet and a replication number indication a number of times the first packet is to be replicated;
performing a second data fetch to fetch second data from a memory buffer, the second data comprising a second packet pointer representing a second packet; and
serially replicating the first packet and the second packet based at least in part upon the replication number and a predetermined threshold value during a clock cycle.
9. The method of claim 8 , wherein serially replicating the first packet and the second packet comprises logically duplicating the first packet and the second packet to generate at least one first replicated packet and at least one second replicated packet.
10. The method of claim 9 , wherein serially replicating the first packet and the second packet further comprises sending the at least one first replicated packet and the at least one second replicated packet to respective output ports of a plurality of output ports.
11. The method of claim 10 , wherein the first data further comprises a vector bitmap, the vector bitmap indicating which ones of the plurality of output ports are scheduled to receive the at least one first replicated packet.
12. The method of claim 11 , wherein the vector bitmap expresses a total number of replications the first packet is to be replicated, wherein the number of replications is a remaining number of replications, the remaining number of replications being less than the total number of replications.
13. A system comprising:
a memory buffer configured to store a first replication number, the first replication number indicating a number of times a first packet is to be replicated, and a second replication number, the second replication number indicating a number of times the second packet is to be replicated;
a plurality of output ports, each output port configured to receive a first replicated packet and a second replicated packet; and
circuitry configured to generate at least one first replicated packet and at least one second replicated packet during the same clock cycle based at least upon the first replication number.
14. The system of claim 13 , wherein the memory buffer is further configured to store a vector bitmap, the vector bitmap indicated which of the plurality of output ports are scheduled to receive the at least one first replicated packet.
15. The system of claim 14 , wherein the circuitry is further configured to direct, during a clock cycle, the at least one first replicated packet and the at least one second replicated packet to a respective ones of the plurality of output ports.
16. The system of claim 15 , wherein the circuitry comprises a plurality of buses, each bus being dedicated to a respective set of the plurality of output ports.
17. The system of claim 16 , wherein the circuitry is further configured to direct, during the clock cycle, the at least one first replicated packet and the at least one second replicated packet to a respective ones of the plurality of output ports via one of the plurality of buses.