IP Library Granted Patent US 8,987,729
Granted Patent B2
US 8,987,729 · App. 13/680,757 · Granted Mar 24, 2015

Semiconductor device and method of manufacturing the semiconductor device

Inventors: Kishou Kaneko (Kanagawa, JP); Naoya Inoue (Kanagawa, JP); Yoshihiro Hayashi (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
H01L27/088H01L29/66477H01L27/1218H01L27/1225H01L27/1237H01L27/124H01L27/1251H01L23/522
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Quick Facts
Patent No.
US 8,987,729
App. No.
13/680,757
Granted
Mar 24, 2015
Kind
B2
Abstract

An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.

Claims (43)

1. A semiconductor device comprising:

a multilayer interconnect layer having a first interconnect layer and a second interconnect layer positioned over the first interconnect layer; and

a first transistor and a second transistor formed by using the first interconnect layer,

wherein the first transistor includes:

a first gate electrode buried in the first interconnect layer;

a first gate insulating film positioned over the first gate electrode;

a first semiconductor layer positioned over the first gate insulating film; and

an insulating cover film positioned below the second interconnect layer and covering the upper surface and the lateral side of the first semiconductor layer, and

wherein the second transistor includes:

a second gate electrode buried in the first interconnect layer;

a second gate insulating film positioned over the second gate electrode; and

a second semiconductor layer positioned over the second gate insulating film, positioned at least partially above the insulating cover film and formed of a material different from that of the first semiconductor layer.

2. The semiconductor device according to claim 1 ,

wherein the multilayer interconnect layer has an anti-diffusion film positioned between the first interconnect layer and the second interconnect layer, and

wherein the first gate insulating film and the second gate insulating film contain the anti-diffusion film.

3. The semiconductor device according to claim 2 ,

wherein the insulating cover film is positioned also below the semiconductor layer, and

wherein the second insulating film has the insulating cover film positioned below the second semiconductor layer.

4. The semiconductor device according to claim 1 ,

wherein the multilayer interconnect layer has an anti-diffusion film positioned between the first interconnect layer and the second interconnect layer,

wherein the anti-diffusion film has a first opening positioned over the first gate electrode, and

wherein the first gate insulating film is positioned in the first opening.

5. The semiconductor device according to claim 1 ,

wherein the multilayer interconnect layer has an anti-diffusion film positioned between the first interconnect layer and the second interconnect layer,

wherein the insulating cover film is formed also over the anti-diffusion film,

wherein a stacked film of the anti-diffusion film and the insulating cover film has a second opening positioned over the second gate electrode, and

wherein the second gate insulating film is positioned in the second opening.

6. The semiconductor device according to claim 1 ,

wherein the film thickness is different between the first gate insulating film and the second gate insulating film.

7. The semiconductor device according to claim 1 ,

wherein the conduction type of the first semiconductor layer and the second semiconductor layer is different from each other.

8. The semiconductor device according to claim 1 ,

wherein the conduction type of the first semiconductor layer and the second semiconductor layer is identical to each other.

9. A semiconductor device according to claim 1 , wherein

the insulating cover film contains one of SiN film, SiO 2 film, SiOC film, and SiOCH film.

10. The semiconductor device according to claim 2 ,

wherein the anti-diffusion film contains at least one of SiN film, SiCN film, and SiC film.

11. The semiconductor device according to claim 1 ,

wherein each of the first gate electrode and the second gate electrode comprises a Cu interconnect.

12. The semiconductor device according to claim 1 ,

wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor layer.

13. The semiconductor device according to claim 12 ,

wherein the oxide semiconductor layer is, InGaZnO layer, InZnO layer, ZnO layer, ZnAlO layer, ZnCuO layer, NiO layer, SnO layer, SnO 2 layer, CuO layer, Cu 2 O layer, CuAlO layer, ZnO layer, ZnAlO layer, Ta 2 O 5 layer, or TiO 2 layer.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2013
From: KANEKO, KISHOU; INOUE, NAOYA; HAYASHI, YOSHIHIRO
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 030651/0945 →
Priority Claims (1)
JP 2011-273229 · Dec 14, 2011 · national
Continuity (1)
Related Publication 20130153887A1 · Jun 20, 2013